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Are Variable Length Arrays Legal in VHDL?


I just wrote a Java program that creates a two-dimensional array of integers. The one-dimensional array defined as "tgl[ 0]" has 25 elements, the one-dimensional array defined as "tgl[ 1]" has 24 elements, the one-dimensional array defined as "tgl[ 2]" has 23 elements, all the way to the one-dimensional array defined as "tgl[ 24]" that has 1 element. Is there some way to do this in VHDL, create a two-dimensional array of bit signals such that each component one-dimensional array of bit signals has a different length from all the others?


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