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I'm regenerating a hps system with the Platform Designer and receive a couple of errors during execution of script generate_hps_sdram.tcl
This is the situation when I click Tool>>tcl scripts..>>hps_sdram_p0_pin_assignments.tcl>>run
Error:Info: *******************************************************************
Error:Info: Running Quartus Prime Timing Analyzer
Error: Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Error: Info: Copyright (C) 2019 Intel Corporation. All rights reserved.
Error: Info: Your use of Intel Corporation's design tools, logic functions
Error: Info: and other software and tools, and any partner logic
Error: Info: functions, and any output files from any of the foregoing
Error: Info: (including device programming or simulation files), and any
Error: Info: associated documentation or information are expressly subject
Error: Info: to the terms and conditions of the Intel Program License
Error: Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Error: Info: the Intel FPGA IP License Agreement, or other applicable license
Error: Info: agreement, including, without limitation, that your use is for
Error: Info: the sole purpose of programming logic devices manufactured by
Error: Info: Intel and sold by Intel or its authorized distributors. Please
Error: Info: refer to the applicable agreement for further details, at
Error: Info: https://fpgasoftware.intel.com/eula.
Error: Info: Processing started: Wed May 20 09:13:14 2020
Error:Info: Command: quartus_sta -t C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl soc_system
Error:Info: Quartus(args): soc_system
Error:Warning (125092): Tcl Script File DDR3_sdram.qip not found
Error: Info (125063): set_global_assignment -name QIP_FILE DDR3_sdram.qip
Error:Warning (125092): Tcl Script File DDR3_sdram.sip not found
Error: Info (125063): set_global_assignment -name SIP_FILE DDR3_sdram.sip
Error:Warning (125092): Tcl Script File ddr3.qip not found
Error: Info (125063): set_global_assignment -name QIP_FILE ddr3.qip
Error:Warning (125092): Tcl Script File ddr3.sip not found
Error: Info (125063): set_global_assignment -name SIP_FILE ddr3.sip
Error:Info: Cleaning up stale assignments...
Error:Error (23031): Evaluation of Tcl script C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl unsuccessful
Error:Error: Quartus Prime Timing Analyzer was unsuccessful. 1 error, 4 warnings
Error: Error: Peak virtual memory: 4630 megabytes
Error: Error: Processing ended: Wed May 20 09:13:16 2020
Error: Error: Elapsed time: 00:00:02
Error: Error: Total CPU time (on all processors): 00:00:02
Error:------------------------------------------------
Error:ERROR: Can't run the Timing Analyzer (quartus_sta) -- Partition Merge (quartus_cdb --merge) failed or was not run. Run the Partition Merge (quartus_cdb --merge) successfully before running the Timing Analyzer (create_timing_netlist -post_map).
Error: while executing
Error:"create_timing_netlist -post_map"
Error: invoked from within
Error:"if { ! [ timing_netlist_exist ] } {
Error: create_timing_netlist -post_map
Error:}"
Error: (file "C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl" line 174)
Error:------------------------------------------------
Error: while executing
Error:"exec $cmd -t [ info script ] $project_name "
Error: invoked from within
Error:"if { ![info exists quartus(nameofexecutable)] || ($quartus(nameofexecutable) != "quartus_sta" && $quartus(nameofexecutable) != "quartus_map") } {
Error: pos..."
Error: (file "C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl" line 110)
Error: invoked from within
Error:"_source C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl"
Error: ("uplevel" body line 1)
Error: invoked from within
Error:"uplevel 1 $cmd "
Error: (procedure "source" line 5)
Error: invoked from within
Error:"source "C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl""
And this is the situation when I click Procssing>>start complication
Error (12252): Border: 2020.05.20.09:07:13 Error: seq: Error during execution of "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error (12252): Border: 2020.05.20.09:07:13 Error: seq: Execution of command "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error (12252): Border: 2020.05.20.09:07:13 Error: seq: child process exited abnormally
Error (12252): Border: 2020.05.20.09:07:14 Error: seq: add_fileset_file: No such file D:/Temp/alt8402_6616470643549882170.dir/0004_seq_gen/hps_AC_ROM.hex
Error (12252): Border: while executing
Error (12252): Border: "add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $file_pathname"
Error (12252): Border: ("foreach" body line 4)
Error (12252): Border: invoked from within
Error (12252): Border: "foreach file_pathname $return_files_sw {
Error (12252): Border: _dprint 1 "Preparing to add $file_pathname"
Error (12252): Border: set file_name [file tail $file_pathname]
Error (12252): Border: add_fileset_file $..."
Error (12252): Border: (procedure "generate_sw" line 18)
Error (12252): Border: invoked from within
Error (12252): Border: "generate_sw $name $fileset"
Error (12252): Border: ("if" then script line 4)
Error (12252): Border: invoked from within
Error (12252): Border: "if {[string compare -nocase $fileset QUARTUS_SYNTH] == 0} {
Error (12252): Border: set top_level_file "altera_mem_if_hhp_qseq_synth_top.v"
Error (12252): Border: add_fileset_file $top_level_fi..."
Error (12252): Border: (procedure "generate_files" line 4)
Error (12252): Border: invoked from within
Error (12252): Border: "generate_files $name QUARTUS_SYNTH"
Error (12252): Border: (procedure "generate_synth" line 3)
Error (12252): Border: invoked from within
Error (12252): Border: "generate_synth altera_mem_if_hhp_qseq_synth_top"
I am using Microsoft Windows [Version 10.0.18363.720]
Quartus installation: LAST_QUARTUS_VERSION "19.1.0 SP0.02std Standard Edition"
I got a completed HDL designed file generated from platform design by my friend. So I can do processing>>start compilation on above. But in platform design phase, there was trouble, too
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Execution of command "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: child process exited abnormally
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: add_fileset_file: No such file D:/Temp/alt8402_526125175150717200.dir/0004_seq_gen/hps_AC_ROM.hex
Error: border: Error during execution of script generate_hps_sdram.tcl: Generation stopped, 3 or more modules remaining
Error: border: Execution of script generate_hps_sdram.tcl failed
Error: border: 2020.05.20.09:19:20 Info:
....
Does anyone have had the same problem or maybe has a solution?
Sincerely,
letternote
Link Copied
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Does your hps system consist of DDR4 memory? We have similar case reported because of the windows 10 update.
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Oh, I didn't write my chip name. my using chip is Altera 28nm Cyclone V FPGA with ARM Cortex A9 on DE1-Soc board.
and this one consists of DDR3 memory.
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The current workaround for it would be use another computer with linux OS for generation, or you may send your design for us to generate it for you
You can attached here or you can refer to your email for the attachment,
Sorry for the inconvenience cause
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Can you try out this solution?
1) https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2018/error--s0--error-during-execution-of---quartus-installation--nio.html
Or
2)
Go to check the jtagserver.exe (same path as in the generate log) whether it is enabled in the firewall for all network types, see below:
jtagserver firewall
You may have to click on the 'Change settings' button with a shield icon on it before the firewall rules are editable - they are locked against being changed by software.
You might need to have the admin to do this.
Thanks,
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Any update?
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Seems like we have patch for this https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2020/fatal--cannot-generate-ip-in-a-windows-evironment-.html.
The error message reported are similar,
ERROR: Found Error => border: 2019.06.13.20:07:57 Info: p0: "hps_sdram" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
ERROR: Found Error => border: 2019.06.13.20:07:57 Error: seq: Cannot locate the Nios II Command Shell. Nios II SBT must be installed to generate UniPHY IP cores.
ERROR: Found Error => border: 2019.06.13.20:07:57 Error: seq: An error occurred
ERROR: Found Error => border: while executing
ERROR: Found Error => border: "error "An error occurred""
ERROR: Found Error => border: (procedure "_error" line 8)
ERROR: Found Error => border: invoked from within
ERROR: Found Error => border: "_error "Cannot locate the Nios II Command Shell. Nios II SBT must be installed to generate UniPHY IP cores.""
Can you try this patch and let us know the result?
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Further investigation, if the patch above does not work. You may use the workaround mention below:
- uninstalled Ubuntu 18.04 (If you have)
- uninstalled wsl
- re-installed wsl
- downloaded latest Ubuntu 18.04 from Microsoft Shop & installed it
- executed following on Ubuntu shell :
sudo apt-get update
sudo apt install wsl
sudo apt install dos2unix
sudo apt install make
sudo apt-get upgrade
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/wslpath---nios--ii-eds-installation-directory-or-nios-ii-project.html
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Just to let you know that we have other customer tested the workaround above and works. closing the thread, thanks

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