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I`m not able to run the counter example on the FPGA.

I tried the example with "build.bat test-fpga".

then this errors apear.

i++ -march=Arria10 counter.cpp -o test-fpga.exe
HLS Generate component ipxact for Platform Designer FAILED.
See c:/Users/JITOU/Desktop/sample/test-fpga.prj/debug.log for details.
Run test-fpga.exe to execute the test.

And this is in debug.log.

2020.09.03.13:22:34 Info: Saving generation log to C:/Users/JITOU/Desktop/sample/test-fpga.prj/components/count/count/count_generation.rpt
2020.09.03.13:22:34 Info: Generated by version: 20.2 build 50
2020.09.03.13:22:34 Info: Starting: Create HDL design files for synthesis
2020.09.03.13:22:34 Info: qsys-generate C:\Users\JITOU\Desktop\sample\test-fpga.prj\components\count\count.ip --synthesis=VERILOG --output-directory=C:\Users\JITOU\Desktop\sample\test-fpga.prj\components\count\count --family="Arria 10" --part=Unknown
2020.09.03.13:22:34 Warning: count_internal_inst: Invalid device name in input file: 10AX115U1F45I1SG
2020.09.03.13:22:34 Error: count: deviceFamily "Arria 10" is out of range: "None", "Unknown"
2020.09.03.13:22:34 Error: qsys-generate failed with exit code 3: 1 Error, 1 Warning
2020.09.03.13:22:34 Info: Finished: Create HDL design files for synthesis
2020.09.03.13:22:34 Info: Starting: IP-XACT
2020.09.03.13:22:34 Info: qsys-generate C:\Users\JITOU\Desktop\sample\test-fpga.prj\components\count\count.ip --synthesis=VERILOG --ipxact --output-directory=C:\Users\JITOU\Desktop\sample\test-fpga.prj\components\count\count --family="Arria 10" --part=Unknown
2020.09.03.13:22:35 Info: Finished: IP-XACT

 

How can I solve this problem?

 

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