i++ counter.cpp -v -march=Arria10 -o test-fpga
Target FPGA part name: 10AX115U1F45I1SG
Target FPGA family name: Arria10
Target FPGA speed grade: -1
Analyzing counter.cpp for testbench generation
Creating x86-64 testbench
Analyzing counter.cpp for hardware generation
Verifying verion information in the included files.
Expecting version 22.214.171.124 for all included files.
Included files passed version check. Checked: none.
Optimizing component(s) and generating Verilog files
HLS Generate component ipxact for Platform Designer FAILED.
This lead to an error, and the output from the debug file:
2020.05.25.22:35:01 Info: Generated by version: 20.1 build 177
2020.05.25.22:35:01 Info: Starting: Create HDL design files for synthesis
2020.05.25.22:35:01 Info: qsys-generate /opt/intelFPGA/20.1/hls/examples/counter/test-fpga.prj/components/count/count.ip --synthesis=VERILOG --output-directory=/opt/intelFPGA/20.1/hls/examples/counter/test-fpga.prj/components/count/count --family="Arria 10" --part=Unknown
2020.05.25.22:35:01 Warning: count_internal_inst: Invalid device name in input file: 10AX115U1F45I1SG
2020.05.25.22:35:01 Error: count: deviceFamily "Arria 10" is out of range: "None", "Unknown"
2020.05.25.22:35:01 Error: qsys-generate failed with exit code 3: 1 Error, 1 Warning
2020.05.25.22:35:01 Info: Finished: Create HDL design files for synthesis
2020.05.25.22:35:01 Info: Starting: IP-XACT
How do I fix this?
There is already answered forum post regarding the same issue ,
Please go through and let us know if it helps
Thanks and Regards