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Hello,
I have a very similar problem as shown in this post thread: System ID on FPGA is not match - Intel Community. I built my simple server example design with an edited Qsys design in Quartus. I created a new project template based on the Simple Server example in the Eclipse IDE. I built the program successfully in Eclipse, but when I try to run it on the NIOS II Hardware it tells me that the System ID and timestamp do not match. The people replying in the linked thread say that I need a license, but I don't know what that means or how to get a license? This is to prevent the Open CorePlus Status popup giving a "Time remaining: unlimited" message when I run the sof file on the board?
The difference between the linked thread and mine is that I have Quartus Prime Version 20.1.1 Lite Edition and I have a MAX 10 FPGA Development Board that I am running it on.
Could I get some clarification on this?
Thank you
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Hello
Welcome to INTEL forum. The NIOS II license is available in the SSLC at no cost. Customer can generate the Nois II license there.
Guidance: https://fpgasupport.intel.com/AlteraLicensing/license/index.html --> Self Service Licensing Center --> Sign up for evaluation or No-cost licenses--> Discontinued - Nios® II/f Processor Intel® FPGA IP (License: IP-NIOS)
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How do the licenses change if I decide to use Nios V?
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Also, I noticed that the license shows for the Nios® II/f Processor Intel® FPGA IP, does it also work for the Nios II/e?
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Also, I though for the lite version of Quartus needs no licenses as shown in the below image.
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Hi
The NIOS V license is also available in the SSLC at no cost/free if you needed a change and used it. The Nios II/e core does not require a special license and is compatible with the free or web editions of Quartus. Additionally, Quartus Lite/Web Edition remains free and does not require a license.
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That's great, but that doesn't resolve my initial problem where the system ID and Timestamp do not match. I thought it had to do with a licensing issue. Since I am using the Quartus Lite Edition, is this not the case then? Thus, do the following instructions not apply?
Guidance: https://fpgasupport.intel.com/AlteraLicensing/license/index.html --> Self Service Licensing Center --> Sign up for evaluation or No-cost licenses--> Discontinued - Nios® II/f Processor Intel® FPGA IP (License: IP-NIOS)
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Hi
Apologize for the long delay as I’m OOO for that week. The issue you are encountering with the System ID and timestamp mismatch, along with the Open Core Plus Status popup, is related to the use of licensed IP cores in the Quartus Prime Lite Edition.
· This error occurs when the System ID and timestamp embedded in the software project do not match those in the FPGA hardware design. This typically happens if the hardware design was modified and not recompiled, or if the software project was not updated with the new hardware system information.
· This popup indicates that you are using IP cores in evaluation mode (Open Core Plus mode), which allows you to use the IP core for a limited time for evaluation purposes. The message "Time remaining: unlimited" means that the IP core is in evaluation mode, but the timer has not started.
Some suggestion to the issue.
Recompile the Hardware Design:
Ensure that you have recompiled the Quartus project after any changes to the Qsys (Platform Designer) system.
Open your Quartus project and compile it to generate the latest System ID and timestamp.
Update the Software Project:
After recompiling the hardware design, update your software project in the Eclipse IDE to reflect the new System ID and timestamp.
In Eclipse, go to Nios II -> Run Configuration -> Target Connection tab.
Click on Refresh Connections to detect the new System ID and timestamp.
Check for Licenses:
If your design uses licensed IP cores, you will need to obtain the appropriate licenses. The Lite Edition of Quartus Prime does not support some licensed IP cores.
You can check the IP cores used in your design and see if any of them require licenses that are not available in the Lite Edition.
Request No-Cost Licenses:
For some IP cores, you might be able to obtain no-cost licenses for evaluation or academic purposes. Visit the Self-Service Licensing Center https://licensing.intel.com/psg/s/ to explore options for no-cost or evaluation licenses.
For academic, Sign into the FPGA Academic Program website and request software licenses and hardware from there.
https://www.intel.com/content/www/us/en/developer/topic-technology/fpga-academic/membership.html
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After following your suggestions I still found the same results.
1. I created the qsys design.
2. I generated the HDL, which created the qsys and sopc files
3. I compiled the entire design in Quartus and programmed it into the MAX 10 FPGA.
4. The pop-up with "Time remaining: unlimited" appeared.
5. I created a new template in Eclipse using the generated qsys and sopcinfo files.
6. After a successful build I went to Nios II -> Run Configuration -> Target Connection tab.
7. I Refreshed Connections to detect the new System ID and timestamp and System ID and timestamps did not match.
Could it be because the message "Time remaining: unlimited" pops-up or is this a separate issue?
Also, how would I know which IP cores need licenses?
Thanks for the help!
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Hi
For checking which IP cores need licenses you could check in assembler report .asm.rpt file.
The assembler report is located in <Project directory>/Output_files/<project_name>.asm.rpt.
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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