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Can't open encrypted VHDL or Verilog HDL file "..path_to_design"/direx2/PCIE
What feature is missing?
Btw: There is no feature "implementation" in our license file as well
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could it be part of ip_base? If yes, how to include 73E1_4F81?
Saw this in our license file, but no 73E1_4F81
7:25:59 (alterad) Rereading license file...
7:25:59 (alterad) Server started on erlh1hjx.ad005.onehc.net for:
7:25:59 (alterad) ip_base (consisting of: 6AF7_00D8
7:25:59 (alterad) 6AF8_00BD 6AF7_00BD 6AF7_00BD
7:25:59 (alterad) 6AF7_00BD 6AF8_00A2 6AF7_00A2
7:25:59 (alterad) C4D5_512A 6AF8_0095 6AF7_0095
7:25:59 (alterad) 73E1_3F40 73E1_3000 73E1_3F10
7:25:59 (alterad) D073_2613 73E1_6A32 73E1_6B32
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Hi
To narrow down this issue. Can you provide your
1) Error message screen shot
2) Machine OS information
3) Quartus version used
4) License.dat file
And for privacy, you can also reply/attach your file in private message.
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1) Files attached
2) CentOS 6
3) Altera Quartus II 9.1
4) attached
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Hi
Thanks for update. Upon checking with customer service team, Could you help to regenerate again a new license.dat file in SSLC. Refer the steps here, Guide to generate license file. And try the new generate license, see how things go.
Thanks,
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Hi,
which PCIe are you trying to compile? PCIe compiler for FPGA without PCIe Hard IP, e.g. for Arria GX needed separate licenses, it's not included in IP base bundle.
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We have not heard from you and It is not recommended to keep a Case idle too long without activities. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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