Arria10 Transceiver Oversampling

[japeters]

Dear Community,

I am trying to set up the MGTs of my Arria 10 GX (10AX115N2F45E1SG) FPGA to send data at a rate of 125 Mbps. This should be the lowest possible rate according to table 3 of the Arria 10 Device Overview. I also found the demo design  no. 19 "Arria10 GX SI Board : 11x Oversampling Design using 4 lanes at 150 Mbps using PRBS". Unfortunately, from the slides included in that demo design, I am not sure how to set up my own transceiver. However, I used it as orientation. 

I set up the respective IP core "Transceiver Native PHY" as TX Simplex with two data channels running at a rate of 1250 Mbps in the standard PCS configuration with an interface width of 10. 
The fPLL receives a 125 MHz reference clock from an oscillator and creates from that a 625 MHz clock. 
I use the "tx_clkout" port from the transceiver to clock my own data generator. It has a frequency of 125 MHz. This output is connected to "tx_coreclkin" input. 

With these settings, the data has a rate of 1250 Mbps, which does not surprise me but leaves me wondering how to achieve the 10x Oversampling?

I also tried to clock my data generator with a 12.5 MHz clock, which I created by using an IOPLL that receives its reference from tx_clkout. So I connected the tx_coreclkin port to the 12.5 MHz clock. But again the observed data rate was 1250 Mbps and not the desired 125 Mbps.

I hope someone of you can help me. Thank you!

[Ash_R_Intel]

Hi,

The example design document says the following:

The channel runs @ 150 Mbps after reprogramming the clock to 150 Mhz. This 150 Mbps is achieved using 11x oversampling (both on the transmit and receive side), the transceiver itself is configured at 1650 Mbps.

Oversampling has to be at both Tx and Rx side. Tx side you will be sending at the rate much higher than required and at Rx also you will have multiple samples of the same data, hence, oversampling.

For your case XCVR will run at 1250 Mbps only but at the Rx side you need to discard extra samples received.

Hope that clarifies.

Regards

[japeters]

Thanks for your answer. I would like to post my solution here that  I found in the meantime.

I managed to set up the MGT such that the data (8b10b encoded) is sent at a rate of 125 Mbps. The 10-bit encoded words are handed over to a module that repeats each single bit 10 times, giving me 100-bit wide words. For example, the three-bit word "101" becomes "111111111100000000001111111111".  These 100-bit words are sliced into 5 20-bit wide words, which are handed over to the MGT. The IP core of the MGT has to be set up so that it can handle the 20-bit words. The set rate is still at 1250 Mbps, and the clock from the fPLL is set to 625 MHz. With these settings, it works. However, I do not know whether that is the best way to implement 10x Oversampling.

[Ash_R_Intel]

Hope your query has been answered. Setting the case to closure for now. However, it will be still open for other community members to comment.

Regards