we are participating in the Innovate Europe design contest and we need to implement a bandpass 4th order butterworth filter on DE1 board (Cyclone II EP2C20F484C7 FPGA) using Quartus II 13.0sp1. We have tried to implement it using the two cascaded IIR biquad structure as shown in this example http://wl.altera.co.jp/support/examples/verilog/ver_butterworth.html setting the biquad coefficents calculated by Matlab. Input is 16bit fixed-point signed value. Our question is: is this the right way to implement a bandpass butter? Are there any other examples or advices that could help us?