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burakduysak
Novice
329 Views

Camera Application on DE2-115

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Hello everyone,

I want to implement a camera application on the Altera DE2-115 board.

I aim to get four different camera output on one screen, here is a very similar project:https://youtu.be/RlrAdS8eaxc, instead of this one I am using an analog camera (CCD PAL). For now, I try to get only one camera output on the VGA monitor.

I am using these IP cores for this project:

Video-in decoder

Audio Video Config

Chroma Resampler

Color-space converter (422 to 444)

2x DUAL CLOCK FIFO

SDRAM CONTROLLER Intel FPGA IP

I couldn't get any data from my fifo_out_data signal. 

Also I am wondering that how can I write avolon package signal into the avalon MM slave which is rgb to sdram in my project. And same for vice versa  which is sdram to fifo_in in my project.

Am I have to deal with crossing clock domain ? , because I am using dual clock fifos I think I don't need to.

I attached my project file. Thanks for any help..

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1 Solution
KennyT_Intel
Moderator
309 Views

If you use the VIP, you may need to use the NIOS to programming the various registers within the different modules as well as for running the RTP stack to stream the compressed

video.


You may take a look at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01133-ip-camera.pdf


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4 Replies
KennyT_Intel
Moderator
319 Views

How do you check your fifo output? Few things to node:


If you were using signal tap, make sure you have written a constrain for it before you start signal tap the signal.


I see that you were using Dual Clock fifo developed by the university program. You may take a look here https://fliphtml5.com/kwrs/tytq/basic to evaluate this is needed from your side.


burakduysak
Novice
315 Views

Thanks for your reply ,

Before implementing that project I tried it that manually, I mean I manually wrote some data into SDRAM then write it to DC FIFO from sdram and read these data from reading side of the DC FIFO. The writing side was 143 Mhz and the reading side was 108 Mhz, I got clear colors on VGA display. I ensure it like that. I hope that was enough.Today I tried to implement video-in example from (ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/14.0/University_Program_IP_Cores/Audio_Video/Video... which is pdf that you shared. But I didn't use Nios II softcore processor, am I have to use it ? I am getting white screen nothing else. Can I do it without Nios II ?

Here is my design.

 

KennyT_Intel
Moderator
310 Views

If you use the VIP, you may need to use the NIOS to programming the various registers within the different modules as well as for running the RTP stack to stream the compressed

video.


You may take a look at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01133-ip-camera.pdf


View solution in original post

KennyT_Intel
Moderator
296 Views

We do not receive any response from you to the previous answer that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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