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Altera_Forum
Honored Contributor I
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Can someone explain a line of code regarding arbiterlock in the pixel_buffer_dma?

I am kind of new to the Avalon buss and it's functions.  

I was studying the Altera UP IP components for Video when I got stuck on understanding how is sets and use the master lock function.  

 

As I read the Avalon Interface specification about the Avalon MM interface, the arbiterlock (nowadays renamed to only "lock") should be asserted when the master wants to lock out other masters from accessing a slave. Is that correct undedrstod?  

 

Can someone then please explain the following line of VHDL code found in "altera_up_avalon_video_pixel_buffer_dma.vhd": 

 

master_arbiterlock <= '0' WHEN ((s_pixel_buffer = STATE_2_READ_BUFFER) OR (s_pixel_buffer = STATE_3_MAX_PENDING_READS_STALL)) ELSE '1'; master_read <= '1' WHEN (s_pixel_buffer = STATE_2_READ_BUFFER) ELSE '0';  

 

As I understand this, arbiterlock is deasserted when the component wants to read from the slave. Shouldnt it be the other way around in this case??? 

It looks like it sets "master_arbiterlock" to '0' when it wants to read, and '1' when no action is performed on the slave.  

It would make sense if "master_arbiterlock" was asserted on '0', but it is declared as asserted on '1' in the *hw.tcl file.  

 

:confused:
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