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Controller IP for DE10-Lite SDRAM

TimSch
Novice
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I'm having trouble to initialize the external SDRAM on the DE10-lite board.

I tried to use the SDRAM Controller Intel FPGA IP which was available for free in qsys until Quartus 20.

Now it seems not to be free anymore and I have trouble using it anyway.

My question is: what would be the *free* way to use the SDRAM without having to write a whole controller on my own when one wants to use the latest Quartus lite version?

I searched for "SDRAM" in the IP components and found that:

TimSch_0-1692109529161.png

It doesn't look like it contains a compatible tool for me or I don't understand them.

Is there any guideline on how to use either one of these tools or the "old" SDRAM Controller in combination with the sdram that is attached to the de10-lite board?

Thanks

Tim

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AdzimZM_Intel
Employee
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Hi Tim,


Please find my answer in points below.


"What do you mean by "need to use own design to interface with the SRAM devices"? I thought that the IP would be the interface to communicate with my SDRAM. What am I getting wrong here?"

  • Yes the IP will create a module or design to interface with the memory device.
  • But in this case, the MAX 10 device has it's own supported IP for memory devices and it's limited to memory protocol.
  • So in this case, you need to create your own memory design or use some example designs available from the board vendor.


"By example design you mean the "SDRAM_RTL_Test" in the Demonstrations directory aren't you? That's a great idea.

To be honest I'm not very familiar with verilog, I only used VHDL yet so I was hoping for some VHDL boilerplate."

  • Yes the example design from Demonstrations directory.
  • Maybe you can use the converter to convert Verilog code to VHDL.


"Am I right that - if I would work in verilog - I could simply copy the "Sdram_Control" entity and use it as sdram controller in other projects? Do you know if I have to consider something before using it in my own design? (I would probably try to translate it to VHDL and use it then)."

  • Yes I think you can copy the design into your design and make the connection similar to example design.
  • The parameter should be matched with the SDRAM device already.


Regards,

Adzim


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AdzimZM_Intel
Employee
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Hi Tim,


The MAX 10 device does supported DDR3, DDR3L, DDR2, and LPDDR2 SDRAM.

These are the IPs available in Quartus for MAX 10 device.

Link for reference: https://www.intel.com/content/www/us/en/docs/programmable/683658/current/external-memory-interface.html

It's does support SRAM but need to use own design to interface with the SRAM devices.


That's why you don't find the SDRAM IP in the Quartus.


There is an example design in the resources section of the DE10-Lite Board.

Link: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=4#contents

You may start to test with that design.


Regards,

Adzim


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TimSch
Novice
1,981 Views

Hi Adzim,

I must admit that I don't understand your answer completely, but I'm a complete beginner with (SD)RAM.

Iassumed that the SDRAM mounted on the board wouldn't be "DDR", so I thought I needed some other Controller IP.

What do you mean by "need to use own design to interface with the SRAM devices"? I thought that the IP would be the interface to communicate with my SDRAM. What am I getting wrong here?

By example design you mean the "SDRAM_RTL_Test" in the Demonstrations directory aren't you? That's a great idea.
To be honest I'm not very familiar with verilog, I only used VHDL yet so I was hoping for some VHDL boilerplate.

Am I right that - if I would work in verilog - I could simply copy the "Sdram_Control" entity and use it as sdram controller in other projects? Do you know if I have to consider something before using it in my own design? (I would probably try to translate it to VHDL and use it then).

 

Thanks

Tim

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AdzimZM_Intel
Employee
1,962 Views

Hi Tim,


Please find my answer in points below.


"What do you mean by "need to use own design to interface with the SRAM devices"? I thought that the IP would be the interface to communicate with my SDRAM. What am I getting wrong here?"

  • Yes the IP will create a module or design to interface with the memory device.
  • But in this case, the MAX 10 device has it's own supported IP for memory devices and it's limited to memory protocol.
  • So in this case, you need to create your own memory design or use some example designs available from the board vendor.


"By example design you mean the "SDRAM_RTL_Test" in the Demonstrations directory aren't you? That's a great idea.

To be honest I'm not very familiar with verilog, I only used VHDL yet so I was hoping for some VHDL boilerplate."

  • Yes the example design from Demonstrations directory.
  • Maybe you can use the converter to convert Verilog code to VHDL.


"Am I right that - if I would work in verilog - I could simply copy the "Sdram_Control" entity and use it as sdram controller in other projects? Do you know if I have to consider something before using it in my own design? (I would probably try to translate it to VHDL and use it then)."

  • Yes I think you can copy the design into your design and make the connection similar to example design.
  • The parameter should be matched with the SDRAM device already.


Regards,

Adzim


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AdzimZM_Intel
Employee
1,924 Views

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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TimSch
Novice
1,897 Views

Hello Adzim,

I finally found a free and configurable SDRAM controller that I could customize to make it work with my device.

If I didn't find them, looking into the demonstrations would have been my next step.

Thank you for that!

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Samuel_EH
Beginner
1,698 Views

Hi TIm,

Could you provide the solution you found? I need it to.

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Samuel_EH
Beginner
1,679 Views

Big thanks for help me, maybe this will be in my final work for graduation, I will cite you and Josh if it happen.

 

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TimSch
Novice
1,654 Views

You're welcome!

I don't want to spam the forum with any more off topic, just one last answer.

 

It seems like we are fellow sufferers. Feel free to open an issue in my git if you have any questions, find a bug or want to exchange ideas about our topics. We'll find a way to exchange less public ways to talk.

 

I wish you much success for your project!

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