In order to simulate it, I've downloaded pll_dynamicphaseshift .qar. But unfortunately ,this design is valid for StratixV. I cannot use StratixV, because I'm using Quartus Prime 18.1 Lite edition.So, do you have an example with CycloneV?
Anyway, I've took some .v files( Test,Example_SM,Test_tb) from the downloaded example and ,in addition, I've generated new PLL_AN.v file .
The data for new generated PLL_AN.v file has been taken from AN661_fPLL_Reconfig.pdf file.
But when I'm trying to simulate project via Native Links, then I'm getting this error:
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" TEST_TB
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs=""+acc"" TEST_TB
# Start time: 12:59:16 on Sep 01,2019
# ** Error: (vsim-3170) Could not find 'TEST_TB'.
# Searched libraries:
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/altera
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/220model
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/sgate
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/altera_mf
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/altera_lnsim
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/cyclonev
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/cyclonev_hssi
# C:/intelFPGA_lite/18.1/ModelSim/modelsim_ase/altera/verilog/cyclonev_pcie_hip
# C:/Alex/my_designs/18_1/PLL_phase_reconfig/Phase_Dyn_004/simulation/modelsim/rtl_work
# C:/Alex/my_designs/18_1/PLL_phase_reconfig/Phase_Dyn_004/simulation/modelsim/rtl_work
# Error loading design
In another words ModelSim cannot find 'TEST_TB'.
But why ModelSim cannot find this file?
