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Hi to everyone! I would like just a block for acquisition
in VHDL language, because i am programming in VHDL,
and the camera code is in Verilog . Thanks
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Hello cdnv,
Verilog and VHDL is just a language to descript your module.
I suggest you read up some syntex on verilog and re-synthesis it to VHDL.
Be mindful to verify your RTL and also test your module using the test-bench.
This will ensure your synthesis is correct.
Please correct me if I am wrong.
Cheers,
- CrimsonLion
