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DE1-SOC: What is default instruction clock frequency of HPS?

Altera_Forum
Honored Contributor II
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Hi, 

 

I wonder couple of things about DE1-SOC board's HPS. 

We use Altera Monitor Program and the project is baremetal based and uses default DE1_SoC_Computer.sof for the FPGA part. 

 

1. What is the clock frequency that ARM instructions are executed? 

2. If I toggle one of the GPIO pin by accessing its address directly, what is the possible square wave frequency that I can get? 

 

ALT_CLK_IN_PIN_OSC1 = 25 MHZ 

ALT_CLK_IN_PIN_OSC2 = 25 MHZ 

ALT_CLK_F2H_PERIPH_REF = 0 

ALT_CLK_F2H_SDRAM_REF = 0 

ALT_CLK_IN_PIN_JTAG = 0 

ALT_CLK_IN_PIN_ULPI0 = 0 

ALT_CLK_IN_PIN_ULPI1 = 0 

ALT_CLK_IN_PIN_EMAC0_RX = 0 

ALT_CLK_IN_PIN_EMAC1_RX = 0 

ALT_CLK_MAIN_PLL = 1850 MHZ 

ALT_CLK_PERIPHERAL_PLL = 1000 MHZ 

ALT_CLK_SDRAM_PLL = 800 MHZ 

ALT_CLK_OSC1 = 25 MHZ 

ALT_CLK_MAIN_PLL_C0 = 925 MHZ 

ALT_CLK_MAIN_PLL_C1 = 370 MHZ 

ALT_CLK_MAIN_PLL_C2 = 462.5 MHZ 

ALT_CLK_MAIN_PLL_C3 = 370 MHZ 

ALT_CLK_MAIN_PLL_C4 = 3.61 MHZ 

ALT_CLK_MAIN_PLL_C5 = 97.4 MHZ 

ALT_CLK_MPU = 925 MHZ 

ALT_CLK_MPU_L2_RAM = 462.5 MHZ 

ALT_CLK_MPU_PERIPH = 231.25 MHZ (Global Timer) 

ALT_CLK_L3_MAIN = 370 MHZ 

ALT_CLK_L3_MP = 185 MHZ 

ALT_CLK_L3_SP = 92.5 MHZ 

ALT_CLK_L4_MAIN = 370 MHZ 

ALT_CLK_L4_MP = 100 MHZ 

ALT_CLK_L4_SP = 100 MHZ 

ALT_CLK_DBG_BASE = 25 MHZ 

ALT_CLK_DBG_AT = 8.3 MHZ 

ALT_CLK_DBG_TRACE = 25 MHZ 

ALT_CLK_DBG_TIMER = 25 MHZ 

ALT_CLK_DBG = 12.5 MHZ 

ALT_CLK_MAIN_QSPI = 370 MHZ 

ALT_CLK_MAIN_NAND_SDMMC = 3.61 MHZ 

ALT_CLK_CFG = 97.4 MHZ 

ALT_CLK_H2F_USER0 = 97.4 MHZ 

ALT_CLK_PERIPHERAL_PLL_C0 = 1.95 MHZ 

ALT_CLK_PERIPHERAL_PLL_C1 = 250 MHZ 

ALT_CLK_PERIPHERAL_PLL_C2 = 1.95 MHZ 

ALT_CLK_PERIPHERAL_PLL_C3 = 200 MHZ 

ALT_CLK_PERIPHERAL_PLL_C4 = 200 MHZ 

ALT_CLK_PERIPHERAL_PLL_C5 = 1.95 MHZ 

ALT_CLK_USB_MP = 200 MHZ 

ALT_CLK_SPI_M = 200 MHZ 

ALT_CLK_QSPI = 370 MHZ 

ALT_CLK_NAND_X = 200 MHZ 

ALT_CLK_NAND = 50 MHZ 

ALT_CLK_SDMMC = 200 MHZ 

ALT_CLK_EMAC0 = 1.95 MHZ 

ALT_CLK_EMAC1 = 250 MHZ 

ALT_CLK_CAN0 = 12.5 MHZ 

ALT_CLK_CAN1 = 12.5 MHZ 

ALT_CLK_GPIO_DB = 32 kHZ 

ALT_CLK_H2F_USER1 = 1.95 MHZ 

ALT_CLK_SDRAM_PLL_C0 = 400 MHZ 

ALT_CLK_SDRAM_PLL_C1 = 800 MHZ 

ALT_CLK_SDRAM_PLL_C2 = 400 MHZ 

ALT_CLK_SDRAM_PLL_C3 = 400 MHZ 

ALT_CLK_SDRAM_PLL_C4 = 400 MHZ 

ALT_CLK_SDRAM_PLL_C5 = 133.3 MHZ 

ALT_CLK_DDR_DQS = 400 MHZ 

ALT_CLK_DDR_2X_DQS = 800 MHZ 

ALT_CLK_DDR_DQ = 400 MHZ 

ALT_CLK_H2F_USER2 = 133.3 MHZ 

ALT_CLK_OUT_PIN_EMAC0_TX = 133.3 MHZ 

ALT_CLK_OUT_PIN_EMAC1_TX = 133.3 MHZ 

ALT_CLK_OUT_PIN_SDMMC = 133.3 MHZ 

ALT_CLK_OUT_PIN_I2C0_SCL = 133.3 MHZ 

ALT_CLK_OUT_PIN_I2C1_SCL = 133.3 MHZ 

ALT_CLK_OUT_PIN_I2C2_SCL = 133.3 MHZ 

ALT_CLK_OUT_PIN_I2C3_SCL = 133.3 MHZ 

ALT_CLK_OUT_PIN_SPIM0 = 133.3 MHZ 

ALT_CLK_OUT_PIN_SPIM1 = 133.3 MHZ 

ALT_CLK_OUT_PIN_QSPI = 133.3 MHZ 

 

 

 

Thanks.
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