Hi guys, I have a problem with my DM9000A project. My project is sending packets from FPGA to PC using only VHDL codes to program. Some parts I copied from internet. Then I used wireshark to calculate sending packets rate but it showed some error. Instead of sending UDP packets from FPGA to PC it does in reverse way. I dont know what's wrong with my code :( Below is my project, target MAC, IP and own MAC, IP are my PC and kit, respectively. Plz help me. Sorry for my bad english :)https://www.dropbox.com/s/ssmigqkoqczchwd/dm9000a.rar
I set my PC's IP is 0A000001 and my FPGA is 0A00000A, it suppose to send packets from FPGA to PC but in wireshark it shows the source is 10.0.0.1 and destination is 10.0.0.255 sending NBNS packets. Unfortunately I am no good (yet) with debugging things. I am really desperate now :(
For what it's worth, seeing a packet with source from your PC and a destination 10.0.0.255 NBNS, is totally unrelated to your FPGA. This is just regular PC (broadcast) traffic.So it sounds like you do not yet have valid packets coming out of your design, and it is not simple like the source/destination fields are wrong.
Sorry, but you need to debug it and come back with a more specific question that someone might have a chance to answer.One easy way to fix it would be to go back to "Some parts I copied from internet" and review what you have done differently, assuming you have good faith that what you found on the internet actually worked in the first place.
it has been a week and I has been checking my project from the beginning. As far as I know, there is nothing wrong with my DM9000A controller block, and I'm still working on UDP/IP block. But as I said before I am f***ing noob, so with 400+ views, I really hope that someone could give me a hand :(