HiIs there a way to get a clock signal from an external device into any PLL clockin on the DE2? I've read that those clockin must be from a dedicated clock, but if I search in the manual of DE2 and the pin planer for the EP2C35F672C6(the FPGA on the DE2), those pins are already use by switches and stuff, not a single one avaible on the I/O connector. How can I set up the PLL to use one of this I/O in the 40 pin connector?, or How can I get into the PLL a signal coming from other device? Thanks a lot!
Please review the schematic for the DE2. There are several versions of this board (DE2, DE2-70, DE2-115)On the DE2, there is an SMA on the board, it connects to pin P26 which is called CLOCK_EXT in the schematic and connects to CLK7 on the FPGA. You should be able to use that. Cheers, Dave
Thanks dwhMy board says just DE2, so I'll use the SMA... Is anything else for configuration to use this for the PLL? I mean, I've created a PLL with the megafunction where do I tell it to use CLK7 or its just by setting the PLL clockin port to CLOCK_EXT in the pin planer? Thanks
--- Quote Start --- Is anything else for configuration to use this for the PLL? I mean, I've created a PLL with the megafunction where do I tell it to use CLK7 or its just by setting the PLL clockin port to CLOCK_EXT in the pin planer? --- Quote End --- You can call the clock port/net anything you like, just so long as you set the pin to P26. For example, I call it clk_sma in my top-level design file. You then connect that net name as the clock input to your PLL megafunction instance. I would recommend creating a counter and use it to blink an LED once per second. If you have the PLL configured correctly, then it'll be pretty obvious. This thread: http://www.alteraforum.com/forum/showthread.php?t=33462 has an example zip file called de2_basic.zip. Download it and follow the instructions. It doesn't have a PLL in the example, but you could add it easily enough. Cheers, Dave
--- Quote Start --- I can't understand what you want to say in the code word of "PLL"...? can you please explain? --- Quote End --- PLL = phase-locked loop http://en.wikipedia.org/wiki/pll Cheers, Dave