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Altera_Forum
Honored Contributor I
729 Views

FPGA programma

Hallo. 

In the line: assign is something wrong. What is the right way for this line? 

Thanks. 

JackR. 

 

module Lab3 (s ,x ,y ,m ); 

input s; //[1:0] s; werkt niet.Geeft s,s0 en s1 

input [7:0] x; 

input [7:0] y; 

output [7:0] m; 

assign m [7:0] = (~s&x)|(s&y) [7:0], x [7:0], y [7:0];  

endmodule
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4 Replies
Altera_Forum
Honored Contributor I
33 Views

Whitout some explanations on how it is supposed to work (what should it do) it's very difficult to guess what you want.

Altera_Forum
Honored Contributor I
33 Views

Hallo amilcar. 

Thanks for the replay. It is for a eight-bit wide 2 to 1 multiplexer. 

 

Figure 3. An eight-bit wide 2-to-1 multiplexer. 

1. Create a new Quartus II project for your circuit. 

2. Include your Verilog file for the eight-bit wide 2-to-1 multiplexer in your project. Use switch sw 17 on the 

DE2 board as the s input, switches sw7−0 as the x input and sw15−8 as the y input. Connect the sw 

switches to the red lights ledr and connect the outputm to the green lights ledg7−0. 

3. Include in your project the required pin assignments for the DE2 board. As discussed in Part I, these 

assignments ensure that the input ports of your Verilog code will use the pins on the Cyclone II FPGA 

that are connected to the sw switches, and the output ports of your Verilog code will use the FPGA pins 

connected to the ledr and ledg lights. 

4. Compile the project. 

5. Download the compiled circuit into the FPGA chip. Test the functionality of the eight-bit wide 2-to-1 

multiplexer by toggling the switch. 

 

Hope this wil help. 

 

Thanks, 

JackR. 

Altera_Forum
Honored Contributor I
33 Views

assign m = s ? x : y;

Altera_Forum
Honored Contributor I
33 Views

Thanks a lot amilcar. 

Best regards. 

JackR.
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