How to see all inputs/outputs in node finder?

SSale9 · ‎11-16-2018

Right now I'm trying to create a system comprised of multiple modules (new to Verilog), and I can only ever see the nodes in the top-level entity when in the node finder. As an example, I have written something that follows the following structure:

module exampleMod1(a, b, c, d)
input a,b;
output c,d;
always @(posedge clk)
begin
//processing a and b
end
endmodule
 
module exampleMod2(e, f, g, h)
input e,f;
output g,h;
always @(posedge clk)
begin
//processing e and f
end
endmodule
 
module exampleMod3(i, j, k, l)
input i, j;
output k,l;
always @(posedge clk)
begin
//processing i and j
end
endmodule

However, if exampleMod1 is my top-level entity (I have selected it as such in the Assignments > Settings > General section) then when I proceed to the Node Finder in my .vwf file and select list, only the nodes in exampleMod1 are shown (a, b, c and d), since it is the top level module. This also means that I can't run a simulation properly, since I can't view the input that I want to as it is neither a or b. How can I correct this to see all inputs and outputs in the project?

AndyN · ‎11-16-2018

If I'm understanding what you are trying to achieve, you need to put a top level wrapper above these modules that will instantiate the modules you want. If you just tell it to use exampleMod1 as your top level, it isn't going to include 2 and 3 in the design.

Something like this:

module topWrapper (a, b, c, d, e, f, g, h, i, j, k, l);
  input a, b, e, f, i, j;
  output c, d, g, h, k, l;
 
exampleMod1 mod1 (
  .a, .b,
  .c, .d
);
 
exampleMod2 mod2 (
  .e, .f,
  .g, .h
);
 
exampleMod3 mod3 (
  .i, .j,
  .k, .l
);
 
endmodule

Hope that helps,

Andy