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I dont wont to save the "space" in SRAM, Help me ?

Altera_Forum
Honored Contributor II
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Hi every body ...  

 

i wrote a code that receive data RS232 and save it on the SRAM ... and its work http://www.edaboard.com/images/smiles/icon_smile.gif  

 

But i have problem...  

i don't wont to save a " space " ,which equal 20 in hex, with the data ...i tried to modify my code but i failed  

 

i dont know what is wrong with my code ?? :/  

 

when i send the data like ( for example) >>>1 then 2 then "space" then 3 then 4  

 

the data saved like this in SRAM >>>> 1 then 2 then "space" then 4  

 

i dont know why it save the "space" and skip 3 >>????  

 

this is my whole project :  

# ##########################################  

 

module serialfun(clk, RxD, RxD_data, nWR,nCE,  

nRD,Address, Data_Bus,LED,Data_In,nUB,nLB,RxD_endofpacket,RxD_data_ready,RxD_idle,WE);  

input clk;  

input RxD;  

output RxD_idle;  

output RxD_endofpacket;  

output RxD_data_ready;  

output nRD;  

output nWR, nCE;  

output reg WE;  

output [17:0] Address;  

inout [7:0] Data_Bus;  

output [17:0] LED;  

output nUB,nLB;  

 

 

///////////////////////////////////////////////////  

//wire RxD_data_ready;  

output [7:0] RxD_data;  

async_receiver deserializer(.clk(clk), .RxD(RxD), .RxD_data(RxD_data), .RxD_endofpacket(RxD_endofpacket),.RxD_idle(RxD_idle),.RxD_data_ready(RxD_data_ready) );  

 

///////////////////////////////////////////////////  

 

always @(posedge RxD_endofpacket)  

if(RxD_endofpacket==1)  

begin  

if ( RxD_data == 8'b00100000)  

WE=1'b0;  

 

 

else  

WE=1'b1;  

 

end  

///////////////////////////////////////////////////////////  

 

//assign Data_Bus = WE? RxD_data : 8'hzz;  

input [7:0] Data_In;  

reg [17:0] Address_In ;  

 

///////////////////////////////////////////////////////////  

 

 

 

MEM_SRAM u0(.Data_Bus(Data_Bus), .Address(Address), .nRD(nRD), .nUB(nUB), .nLB(nLB),  

.nWR(nWR), .nCE(nCE), .Address_In(Address_In), .Data_In(RxD_data),.LEDR(LED),.RxD_endofpacket(RxD_endofpacket),.WE(WE));  

 

 

endmodule  

 

# #############################################  

 

module MEM_SRAM (  

Data_Bus, // Data Bus  

Address, // RAM Address  

nRD, // RAM Read Enable  

nWR, // RAM Write Enable  

nCE, // RAM Chip Enable  

nUB, // RAM Upper Byte  

nLB, // RAM Lower Byte  

Data_In,  

Address_In,  

RxD_endofpacket,  

LEDR,  

WE,  

clk); // Write Enable  

 

output reg [17:0] Address; // RAM Signals // include  

inout [7:0] Data_Bus;  

output nRD, nWR;  

output nUB, nLB;  

output nCE;  

input WE; // Write Enable  

input [17:0] Address_In ;  

input [7:0] Data_In;  

input RxD_endofpacket;  

output [17:0] LEDR; // include reg  

input clk;  

assign nUB = 1'b1; // Disable Upper Byte  

assign nLB = 1'b0; // Enable Lower Byte  

assign nCE = 1'b0; // Enable Chip  

assign nRD = 1'b0; // Read Enable  

assign nWR = !WE; // Write Enable  

 

 

assign Data_Bus = WE? Data_In : 8'hzz;  

 

always @(posedge RxD_endofpacket)  

if(RxD_endofpacket==1)  

begin  

if(WE==1)  

Address <= Address + 1;  

 

//else  

//Address <= Address + 0;  

end  

 

assign LEDR = Address;  

 

 

endmodule 

 

 

 

 

PLZ... help me http://www.edaboard.com/images/smiles/icon_sad.gif
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