I have a compile error in quartus II when I try to do a counter with asynchronous reset. The error comes from the sensitivity list of the always process. The part of the code is as follows:
always @ ( posedge iCLK, iRST_n )
if ( iRST_n == 0 )
oCOUNT = 0;
The error that the quartus II gives me is the following:
Error (10122): Verilog HDL Event Control error at contador.v(54): mixed single- and double-edge expressions are not supported
The question is: How can I implement an asynchronous reset on a counter in verilog?
You may checkout the webpage below to help you on the Verilog design.
Other than that, our Quartus tool has a variety of Verilog design template in which you can just pop it into your project and use it right away.
In the new created Verilog .v file, right-click on the black space to opens the context menu, scroll to Insert Template, a window Insert Template will pop up, choose Verilog HDL > Full Designs > Counters > Binary Counter.
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