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Altera_Forum

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01-17-2009
05:03 AM

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Implementation of Digital PID controller in FPGA

I'm trying to implement a PI controller in FPGA using schematic entry method in altera quartus II . I'm using the following equivalent PI controller equation,

c(n) = c(n-1)+kp*(e(n)-e(n-1))+Ki*T*e(n-1) where, c(n) = controller output Kp= proportional constant Ki=integral constant e(n)=Reference -actual input T=sampling period I'm implementing it for 8 bit data. I couldnot implement c(n-1) in the above equation using schematic entry. Can someone help me implement this? I would be grateful if you can suggest me other ways of implementing PI controller like in VHDL.Link Copied

30 Replies

Altera_Forum

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01-17-2009
05:27 AM

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Altera_Forum

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01-17-2009
06:57 AM

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gmpstr,

Thanks a lot for response. I used D type flip flop and I sucessfully implemented kp*(e(n)-e(n-1))+Ki*T*e(n-1) but once I took the c(n) and pass it through D type flip flop to get c(n-1) and add to above, my problem started. The value of c(n-1) is always zero though it acutally is not and the result is just always equal to kp*(e(n)-e(n-1))+Ki*T*e(n-1). During synthesis, I got the following warning, Warning (14130): Reduced register "lpm_dff0:inst9|lpm_ff:lpm_ff_component|dffs[0]" with stuck data_in port to stuck value GND Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "output[0]" is stuck at GND Maybe this will help you understand my problem. I hope to get feedback from you in this matter.
Altera_Forum

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01-17-2009
09:11 AM

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Altera_Forum

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01-17-2009
01:43 PM

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Altera_Forum

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01-17-2009
02:32 PM

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Altera_Forum

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01-17-2009
08:34 PM

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Altera_Forum

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01-18-2009
06:46 AM

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Warning (14130): Reduced register "lpm_dff0:inst9|lpm_ff:lpm_ff_component|dffs[0]" with stuck data_in port to stuck value GND

Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "output[0]" is stuck at GND These warnings make sense after looking at the schematic. The two multipliers before the add are doing a multiply by 2 so the result will always be even, thus bit 0 will always be 0. Also noticed that The two dff on the top left(inst1 and inst2) are 16 bit but should be 8bit. When I double click them, the megawizard shows them as 16 bit. Not sure if this is a problem. I fixed that issue and ran a modelsim simulation and the simulation shows data coming out of the dff of inst9. synthesized_wire_11 is the output of dff(inst9)
Altera_Forum

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01-18-2009
08:59 AM

147 Views

Altera_Forum

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01-18-2009
01:16 PM

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--- Quote Start --- Also noticed that The two dff on the top left(inst1 and inst2) are 16 bit but should be 8bit. When I double click them, the megawizard shows them as 16 bit. Not sure if this is a problem. --- Quote End --- The width is automaticly set to 8 in compilation, even without causing a warning. This is a special feature of schematic entry evaluation, I think. It also infers a multi-bit register from a single bit one. --- Quote Start --- But when I tried to simulate the schematic with the corrections you mentioned with a waveform file, I got correct result for 2 periods only. --- Quote End --- I see, that your simulation output has 8 bit. I don't understand what you connected here, cause your design has a 16-bit output. Generally I see two problems. Controller deviation signal e is by it's nature of SIGNED type, no matter what your input signals are. To my opinion it's advisable, to use SIGNED for all signals throughout a PI controller, also for coefficients to avoid type confusion. The

Altera_Forum

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02-06-2009
07:20 PM

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Hi everyone. I'm also triyng to implement a PID in quartus schematic. Does anyone knows ho to make a correct saturation for adders? i've thinked about use multiplexer with index bit carry and bit overflow.

thank you for your help
Altera_Forum

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02-06-2009
09:42 PM

148 Views

I'm using a package of extended arithmetic functions for such purposes. Basically I leave it to the compiler to find an appropriate way to realize the intended behaviour. You may want to compare the achieved effectivity with handcoded saturation arithmetic, I'm satisfied with it up to now.

```
FUNCTION SUM (X1,X2: SIGNED) RETURN SIGNED IS
VARIABLE S:SIGNED(X1'length-1 downto 0);
BEGIN
S:=X1+X2;
IF X1>=0 AND X2>=0 AND S<0 THEN
S:= (others => '1');
S(S'left):='0';
ELSIF X1<0 AND X2<0 AND S>=0 THEN
S(S'left-1 downto 0):= (others => '0');
S(S'left):='1';
END IF;
RETURN S;
END;
```

Altera_Forum

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02-07-2009
06:10 PM

148 Views

Altera_Forum

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02-08-2009
12:09 PM

148 Views

Hi all,

Te code of FvM is well written but I am not sure what is its purpose. You only need to clip (saturate) if you are going to discard one or more MSBs. If you discard LSBs then there will never be the need for saturation, possibly you may go for rounding. In short: Truncation of one LSB = divide by 2 so no clipping needed but rounding. Truncation of one MSB is relatively = multiply by 2 because you would discard one LSB bit less so it needs clipping To implement saturation in schematic or HDL: Just test the MSB you want to discard: if it equals the opposite of sign bit then fill up data with that opposite. Note however, in many real systems you should avoid clipping as it affects signal integrity.
Altera_Forum

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02-08-2009
12:35 PM

148 Views

Simply, when adding numbers without providing extra result bits, the result may overflow to opposite sign, e. g. in case of an integrator

`integ <= integ + x; `

In most real control applications, overflow results in fatal failure, e. g. with said PID controller. Saturation arithmetic prevents from this situation. `integ <= SUM(integ,x);`

Altera_Forum

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02-08-2009
12:48 PM

148 Views

Hi FvM,

Thanks for the clarification, I agree totally that in cases of feedback overflow will occur and be fatal. This saturation is different from my clipping. We better say overflow protection. Apologies, I can see now what your function is doing, in effect precomputing to prevent overflow. it seems like DSP Vs control systems conflict.
Altera_Forum

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02-08-2009
01:41 PM

148 Views

Hi POWERGUI

To sum up, I hope the following method will work: (we only need saturation if there is feedback. If there is no feedback then we can accommodate the result). Assume adder inputs are x1, x2 each 8 bits 2's complement and adder result is S of 9 bits. for feedback x2 = S(8) & S(6:0). i.e. discard S(7). This brings us back to the concept of MSB discarding algorithm, thus: if S(7) is opposite S(8) then fill up all S(or x2) with opposite of S(8).
Altera_Forum

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08-18-2010
10:24 AM

148 Views

s ur controller working fine now...im supposed to implement a PID controller in spartan kit...

Altera_Forum

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08-25-2010
07:49 AM

148 Views

Hi !

I want to implement PI Controller in FPGA SPARTRAN 3e kit, using VHDL. Can you please guide me . I am very new in this field. I studied VHDL 3 years ago, and now i have to implement this task. i have to brush bup my VHDL knowledge. Can you guide me step by step. i will be really obliged. also i have code in matlab for same PI controller but i have to convert that to VHDL. Now it depends should i convert that to vhdl. or else i should write a new code. Hope to listen from you. :)
Altera_Forum

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02-20-2012
01:19 AM

148 Views

me too i'm working on that but as i see no one response

Altera_Forum

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02-20-2012
10:04 AM

19 Views

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