LVDS-Rx IP (DE10 SoC-Cyclone V) interfacing with external ADC : Error in compilation & clock routing

[santosh2uu2]

We're using a ALTERA Cyclone V DE10-SoC board and need to interface FPGA “altlvds_rx” IP with an external ADC's LVDS outputs (data, high speed clock, low speed clock).
We have tried directly connecting the FPGA pins (LVDS pair) to the “altlvds_rx” IP (Pin: “rx_in”, “rx_inclock”, “rx_enable”) for this purpose.

Issues:
1. When I instantiate “altlvds_rx” with Data and clock pins (Pin: “rx_in”, “rx_inclock”, “rx_enable”)
as the top module pins, and tried to compile, In Analysis & Synthesis step it showed:
            • “WRITECLK” and “LOADEN” not properly connected.

Request:
• How can we correctly interface external ADC’s LVDS signals (data, high speed clock, low speed clock) to “altlvds_rx” via FPGA pins ?
• Any peripheral IP should be connected between Top pins (FPGA LVDS pair) and “altlvds_rx” pins (“rx_inclock”, “rx_enable”) to get rid of compilation error and also have successful routing ?
• Example designs or suggestions to resolve these errors and successfully interface FPGA “altlvds_rx” IP with external LVDS ADC outputs ?
Any guidance would be greatly appreciated.

[FvM]

Hi,
generally, it would be helpful to get a complete problem specification:
- Quartus version
- SERDES configuration details
- intended RX clocking method

You have apparently set SERDES RX module to external PLL operation without connecting a PLL (won't be possible for a top level module). That doesn't make much sense because you most likely don't have fast and slow clocks (inclock and rx_enable) with appropriate timing.

[WZ2]

Hi there,

1. For this IP, the example design can typically be generated by selecting the "Generate Example Design" option in the IP parameter editor. You may try generating it under a Cyclone 10 or Arria 10 device — the IP itself is the same across these devices.
2. Regarding the three pins you asked about, their connection method largely depends on your specific IP configuration. Based on your question, I assume you're trying to use an external PLL? Without knowing the exact IP settings, I can only make some general assumptions. The Clock input should be connected to a pin that supports clk_in functionality — please refer to the device's pin list to ensure compatibility.

Let me know if you can share more about your configuration — I’d be happy to provide more specific suggestions.

Best regards,

WZ