Lab 12 Part II Noise Filtering

Altera_Forum · ‎08-13-2017

Hi everyone!

I've been trying to make noise filter for input mic as requested in Lab 12 but I've been having some really strange issues.

Lab link ftp://ftp.altera.com/up/pub/altera_material/12.0/laboratory_exercises/digital_logic/de2-115/verilog/...

So what I do is whenever I got input signal I divide it by 8 and write it in FIFO. On the output I always keep sum of all FIFO registers.

The strange thing that happens is, that it is working perfectly fine when I am not dividing by anything (Just outputing the sum of all registers), and when I am dividing by 8 I only get noise as the output.

Does anybody have any idea what might cause this issue ?

Here is my code in case you couldn't understand what I've been saying :D


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module noise_filter # (
    parameter DATA_WIDTH=24, 
    parameter N = 4
)
(
    input write,
    input clock,
    input  data_in,
    output done,
    output  sum
);
    reg  summed;
    reg  counter;
    reg isDone;
    reg  fifo ;
    integer i;
    initial
    begin
        counter = 0;
        summed = 0;
        isDone = 0;
        
        for(i = 0; i < 2**N; i= i+1)
        begin
            fifo = 0;
        end
    end
    
    always @(posedge clock)
    begin
        if(isDone == 1)
        begin
            isDone <= 0;
        end
        else if(write == 1)
        begin
            counter <= counter + 1;
            fifo <= {{N{1'b0}}, data_in};
            summed <= summed - fifo + data_in ;
            isDone <= 1;
        end            
    end
    assign sum = summed;
    assign done = isDone;
endmodule

So long story short, this outputs just random noise, and with this change


  fifo <= data_in;
  summed <= summed - fifo + data_in;

it works perfect.

Thanks everyone!