Hello,I need a help to solve the first part of exercise 12, Basic Digital Signal Processing. I'm using the libraries provided "lab12_design_files." Insert the following code in the correct area. --YOUR CODE GOES HERE process(read_ready, write_ready, read_s, write_s) is -- Declaration(s) begin if (read_ready='1' and read_s='0') then read_s<='1'; if(write_ready='1' and write_s='0') then write_s<='1'; writedata_left <= readdata_left; writedata_right <= readdata_right; end if; end if; read_s<='0'; write_s<='0'; end process; But the program does not work, does not give errors. But no more sound from the microphone to the speakers. Thanks, Filipe Nunes
Hi, where does "lab12_design_files" come from ? Could you precise more ?Your second "if ... end if" might not be nested, I guess. You get a process that always gives
read_s<='0'; write_s<='0';because of the last two lines.:oops: So, it is very (very, obviously and drastically) simplified by the compiler/synthesizer please review vhdl basics : vhdl is not a programming language:D Draw a logic schema on paper first.
Hello mmTsuchi.Thank you for your help. Sorry for my mistakes, but now I started programming in VHDL, so knowledge is not much. The file "lab12_design_files," withdrew from the following link: "ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Laboratory_Exercises/Digital_Logic/DE2-115/vhdl/" I need to get the microphone sound and send it to a column, to apply a filter in the future. I have urgency to solve this problem, which seems basic, but can not solve. Without solving this first part, I can not achieve the objective of the work is to apply an FFT filter.
First, make a schema with logics. (more complex schema needs good writing)I guess you want to copy readdata_left to writedataleft and same thing for 'right' You might use a synchronous logic (recommended) by using process(clk) because of possible glitches. look for "process(clk)" or "synchronous process) even in quartus help Something like :
process (clock_50) begin if rising_edge(clock_50) then -- not verified at all -- if(write_ready='1' and write_s='0') then write_s<='1'; writedata_left <= readdata_left; writedata_right <= readdata_right; end if; end if; end process;
@noa234ham, sorry to remind you : On the 1st post (http://www.alteraforum.com/forum/showpost.php?p=151553&postcount=1) read_s and write_s are always '0' after synthesis.He should try working examples to see if hardware and software are OK. they should exist.
Hey mates..I have just started to work on Quartus..I have to do this exercise as a part of my course..Can you please guide me on how to approach things?I dont have the starterkit kit which is mentioned in the last line of Page 2 on this assignment..I was trying to setup the audio video configs via the SOPC builder..but all to vain.. I'm terribly disappointed having no tutor to guide on this..Please help if you get time..
Hi, please don't make multiple posts.I don't know those starter kits but they should give a "prework" which drives you where you can write your code. so search for starterkit you mentioned. Else you will probably "burn out" (you have to know pins, to (re)create SOPC system for this exercise, etc ) you should have a working basic example in what you are been given. quartus is a tool which can synthesize and configure fpgas
vhdl is vhsic hardware description langage (not a programming langage) i suggest you good practice of vhdl (see on altera, doulos...)
sopc an oether tool integrated with quartus
nios ii a processor Have you tried my code in #5 (http://www.alteraforum.com/forum/showpost.php?p=151641&postcount=4) ? PLease could you post the entire file ? (we don't do homeworks for you, but advise you :-)) EDIT : Sorry for confusing fmvnunes and azonegrpz :oops: :D
What is exactly your problem :* you have difficulties to write the code. It is quite simple here. I won't answer about that. It is the alphabet of design. If you don't success, change job :-) * you get compilation errors * no compilation error, but configuration failure * success configuring but no working ?
for someone here: I think we should help each other in this forum, so it will be better if all of us can provide the solution not creating more problem and questions
If you give one solution "as is", fmvnunes and lxpool will just copy-and-paste without understanding.I guess this exercise is very very very basic (not carefully read the "how to" of the codec). Just make D flip flop (no resample here, just copy input to output). It is the "hello world" of VHDL. @azonegrpz : it may be an other problem that we can bring solution.
I also have a question regarding this lab. When I was trying to the pin assignment, I got this huge list of pins that I needed to assign, like hex display, leds,... Which one's do I need to assign? Is there a pin assignment sheet for this lab? Also, what does it mean for "ready_signals" to be asserted? Does that mean we raise the value to high or something?I don't understand what this mean, "The ﬁrst element of the buffer is always visible on the readdata left andreaddata right outputs when the read ready signal is asserted. The next element can be read by asserting the read signal, which ejects the current sample and a new one appears one or more clock cycles later, if read ready signal is asserted." I tried to implement this by using if statement and process, but I don't they want us to use them since you have to include libraries to do that, and they won't work in that code. Any ideas? Thanks.
Hello! I had a problem with the 3rd part of laboratory exercise, namely I cannot understand as the scheme shown in drawing 6 should work. Where exactly noise is filtered, what from itself the FIFO buffer, its realization in Quartus II represents, somebody Can help?
Many thanks, itself everything understood.Why such forum of the response is necessary on that not to wait? Оr here one haughty lazy bastards who consider to respond below the advantage sit? BURN IN THE HELL!
I was working through this same lab exercise 12.This code works ... writedata_left <= readdata_left; writedata_right <= readdata_right; write_s <= '1'; read_s <= '1'; This is fine since it echoes the read-in data to the write-out buffers, and then asserts the write_s and read_s so that the codec knows the read and write are done. However, that is not all that the exercise asks for. It includes this: "You should take care to read data from and write data to the Audio CODECInterface only when its ready signals are asserted. " So I was attempting to work out that second part. However I have found no code that accesses read_ready = '1' or write_ready = '1' that functions. The only thing I've found that works is my simple code above, which doesn't exactly complete what is being asked. Here is just one example of something that doesn't work, though I've done many many combinations ... process(CloCK_50) begin if read_ready = '1' and write_ready = '1' then writedata_left <= readdata_left; writedata_right <= readdata_right; write_s <= '1'; read_s <= '1'; end if; end process; Removing references to write_ready and leaving read_ready, doesn't work. vice versa, doesn't work. This works, but the references to read/write_ready have been removed. process(CloCK_50) begin --if read_ready = '1' and write_ready = '1' then writedata_left <= readdata_left; writedata_right <= readdata_right; write_s <= '1'; read_s <= '1'; --end if; end process;
Hi, I haven't look at the schematic of the board neither functionnal chronogram nor truth table. So I may be wrong.But it sounds quite trivial : read data from one component and write data to an other component. Even if we talk about one component : codec but it can be considered as 2 independant components : coder and decoder. In your code above, you wrote process(clock_50) but clock_50 is not used in the process. First draw a very simple schema with D flip flops and translate it to VHDL. VHDL is a hardware description language. You spent too much time by trying to make it work by "trial and error". I hope the board is functionnal ;-)
-- one clocked process to read data from codec process(CloCK_50) begin if rising_edge(clock_50) then if read_ready = '1' then -- ... read_s <= '1'; end if; end if; end process; -- one other process to write data to codec process(CloCK_50) begin if rising_edge(clock_50) then if write_ready = '1' then writedata_left <= readdata_left; writedata_right <= readdata_right; write_s <= '1'; end if; end if; end process;@sethjones : could you put the scheme
--- Quote Start --- Hi, I haven't look at the schematic of the board neither functionnal chronogram nor truth table. So I may be wrong. But it sounds quite trivial : read data from one component and write data to an other component. Even if we talk about one component : codec but it can be considered as 2 independant components : coder and decoder. In your code above, you wrote process(clock_50) but clock_50 is not used in the process. First draw a very simple schema with D flip flops and translate it to VHDL. VHDL is a hardware description language. You spent too much time by trying to make it work by "trial and error". I hope the board is functionnal ;-) --- Quote End --- I agree that it sounds trivial, and when written trivially it works. Yet as soon as I check read_ready or write_ready, it fails. The board is working fine, it is a new DE2-115 board. Without checking read_ready and write_ready the code echoes audio in to out as expected. Clear and at full volume. Referencing process(Clock_50) makes no difference, I can ignore it or not, the code works or doesn't work only based on read_ready or write_ready. I just put that Clock_50 in so I could add a "process" statement (and in turn an 'if' statement to check read_ready) and not get a compile error. I've tried making the process dependent on other signals. It works or doesn't only based on read/write_ready. I've tried code similar to what you've got above, two separate processes, one reading and one writing. I added an extra variable so that the reading process could pull the data in when it was available and the write process had somewhere to write it out from. It made sense, but I was using read_ready and write_ready, so none of it worked. As soon as make my code dependent on read_ready and write_ready, it fails. It would be nice if someone with a DE2-115 board and more experience than I've got could run a real test, or else message me the official solution so I could try that and see what I'm missing. I would really love to see a verified working solution that references read_ready/write_ready, as the lab requires.
Hi, Whoua ! lots of trials.Nice to get it works, you may be lucky. --- Quote Start --- I've tried making the process dependent on other signals. --- Quote End --- Mostly VHDL design employ process(reset_n, clock) and other combinational logics. The clocked process insure that the design IS SYNCHRONOUS. Making a design by using only combinational logics needs very (too) much rigorousness (to avoid glitches, latches, ringing....). I think 0.000000001% work with this. If you make the process dependent on other signals, you build combinational logics. :-( Maybe Read_ready and write_ready are asserted low !? Sometimes there are errors in manuals.