Memory(FPGA) to Memory(HPS SDRAM) data transfer using DMA

[Harsath]

Ultimate Goal:

I am using a DE1-SoC board, to collect the data from and external ADC and store it in SoC Board.

First I am collecting data from ADC to FPGA On-Chip RAM (size10 kB, width 32 BIT ) through SPI and LVDS protocol successfully. Data in FPGA memory is overwritten by the continuous data streaming and ultimatelty transfering and storing full length data in HPS SDRAM.

Planned Topology:

To store the ADC sampled data for 1 second time, I was trying to transfer the data in chunks (size 5kB) from FPGA On-Chip RAM (size10 kB, width 32 BIT ) to HPS SDRAM (size 1 GB) through "DMA Controller Core" using AXI Bus of 128bit.

DMA is controlled by HPS using h2f_axi_master, DMA read_master connected to FPGA On-Chip RAM (Port 1 used by DMA and Port 2 used to store data) and DMA write_master connected to f2h_sdram0_data.

Present Testbench:

Currently I am focused on collecting 50kb data (32bit width) to HPS SDRAM as 5kB chunks from an 10kB FPGA On-Chip RAM (FPGA On-Chip RAM content is overwritten 5 times) using DMA and AXI Bus.

ADC Sampling rate = 1MSPS (1 sample = 32bit width)

FPGA Onchip RAM Utilization = 10kB size ( 32bit width, 2560 Address Locations)

HPS MPU Frequncy = 925MHZ
AXI Clock Frequency = 50MHz

AXI Bus width = 128 bit

DMA Clock Frequency = 50MHz

Expected HPS SDRAM Utilization = 50kB size ( 32bit width, 2560*5 Address locations)

Issues:
I have writen a code in HPS to collect 10kB data as 5kB chunks in a single loop and made 5 iterations to collect and store 50kB data in SDRAM.
When I print the data from the SDRAM, the initial 40kB data is lost and only the last 10kB data is present for the entire 50kB in SDRAM with discontinuties in between and repetition of last 10kB data.

Request:
Can u please VERIFY/ REVIEW the above process FLOW and guide US ON ADC data collection and storing in HPS SDRAM using DMA.

P.S. - Attached HPS C Code, Qsys file, DMA Controller Core Documentation.

If possible provide alternative methods / additional ip requirements / example project for the memory(FPGA) to memory(HPS SDRAM) data transfer using DMA for stream data from ADC.

[khtan]

Hi Harsath,

Thanks for using Altera forums. 

For the queries above, could you refer to the datamover design example that showcase using fpga to hps bridge and accesses to SDRAM controller if you have already certified that reading data from ADC have no issues, just the storing and reading back from SDRAM portion.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html

some alternative info I found

https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HPS_peripherials/FPGA_addr_index.html

https://www.rocketboards.org/foswiki/Projects/Datamover

Thanks

Regards

Kian