Pixel Buffer DMA Controller (altera_up_avalon_video_pixel_buffer_dma) generates Verilog HDL with syntax error

BLee15 · ‎09-19-2019

For example, when "Default Buffer Start Address" and "Default Back Buffer Start Address" is set as 0xFF010000, generated Verilog file contains following lines:

parameter DEFAULT_BUFFER_ADDRESS		= 32'd-16711680;
parameter DEFAULT_BACK_BUF_ADDRESS	= 32'd-16711680;

which causes the following errors:

Error (10170): Verilog HDL syntax error at core_video_pixel_buffer_dma.v(68) near text: "-". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at core_video_pixel_buffer_dma.v(69) near text: "-". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "core_video_pixel_buffer_dma" at core_video_pixel_buffer_dma.v(29) due to previous errors

Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition

SengKok_L_Intel · ‎09-20-2019

Hi,

This looks like if the MSB bit is "1", it represents a negative value, and somehow it added a "-" in the Verilog file and which is incorrect.

To prevent this problem, one of the workarounds is don't set the MSB bit (32nd bit) to "1". For example, 0x7f010000.

Regards -SK

BLee15 · ‎09-20-2019

I applied this workaround and it works as expected.

Nevertheless, please consider this as bug and fix code generator script.

SengKok_L_Intel · ‎09-20-2019

Thank you for the feedback, and this is glad to see this workaround work for you.