Intel® FPGA University Program
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Problem: DE1-SoC Audio Codec

Honored Contributor II

Hello everyone. I'll start by saying that my english sure it's not the best, i apologise for that; but i'll try anyway to be as clear as possibile. 


I'm trying to realise a project on my DE1-SoC which consists in capturing low frequencies sounds through a microphone, and later process those sound. Ideally it should be used to capture and process biological sounds, but that doesn't matter right now. 


So I'm having an issue with the University Program Audio IP and eventually with the Audio and Video Config one. 

So I've started from the altera GHRD, and then using qsys I added three IPs: university program's Audio and Audio and Video config and Audio Clock for DE-series board. 


I generated the HDL from this qsys, modified the ghrd_top.v file in order to add my peripheral devices and then i generated the header files using the sopc-generate-header-file command. So i have the hps_0.h file to include in my C program in order to access the peripheral. 


So in my C file I open the peripherals mapping the lwh2f bridge, and evaluating all the IP's base addresses. 

According to the Audio core data sheet, it should have four registers: 

1) a control register, 

2)a read-only fifospace register, 

3)leftdata register, 

4)rightdata register, 


so as first thing i set the third bit of the control register to 1, because reading the description on the data sheet it says that setting that bit to 1 means clearing the audio core input fifos, which is what i want to do before starting the acquisition. 

In order to do so i write 0x4 in that control register (*audio_addr=0x4;); then i need to read the fifospace register, and that is were i've problems, because, reading the data sheet, the fifospace LSBs should indicate the number of words of incoming audio data in the left and right channel FIFO's, so by reading it different times i should expect a growing value till the number of words reaches the saturation level which should be 128. 

Instead each time i print the content of that register it is 0x00000000. 


So I checked the audio and video config because it seems to me that the auto initialization is failing; even this core has four registers: 

1)Control register, 

2)Status register, 

3)Address register, 

4)Data register 


So i wrote 1 in the first bit of the control register (*audio_cfg=0x1), becuse this should reset the core and re initializes the devices, but when i printed the status register (audio_cfg+1), it was 0x00030003 which is not what i expected beacuse the first bit being high means, according once again to the data sheet, that "an error occurred while transmitting the data". 



While searching for a solution, in the DE1-SoC user manual, in the audio codec section I noticed that if the HPS_I2C_CONTROL signal is set to 1, the HPS is connected to the peripheral and not the FPGA, so this might be the problem, infact i checked the default status of the HPS_I2C_CONTROL by connecting it to a LED and it appears to be high.  

So a possibile solution could be, maybe, to set that signal to 0. 


The problem is that it is connected tu a GPIO, as evidentiated in my ghrd_top.v file  


.hps_0_hps_io_hps_io_gpio_inst_GPIO48 ( HPS_I2C_CONTROL), // .hps_io_gpio_inst_GPIO48 


So reading the Cyclone V Hard Processor System Technical Reference Manual, i noticed that there's a GPIO used to input or output data, which is the gpio_swporta_dr; I added it's base address to my C program and i tried to set all 32 bits of the gpio1 module to 0; but when i execute my program on the DE1-SoC (i build the binaries with eclipse for DS-5, then i use scp to copy the file onto the board and in the end ./ to execute it) it gives me a Segmentation error right after the Open peripherals. 


So right now it seems that i'm trying to write in somewhere i can't, someone knows how to solve this? 


By the way i'm not sure this is the best solution, but is the one i came up with, so i'm happy to hear completely different ideas for a solution. 


Thanks in advance.:)
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5 Replies
Honored Contributor II

GPIO48 from the HPS controls the I2C multiplexer - switching it between the either the FPGA or the HPS. 

When this signal is high, the I2C bus is connected to the HPS. When it is low it is connected to the FPGA. 

See page 26 of the DE1-SoC schematic from the Terasic system CD. 


The segmentation fault is a bug in your program and nothing to do with this. 


(Sorry - just noticed the date of your question, but I'll post this anyway :)
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Honored Contributor II

Hello, I was curious if you were ever able to to switch the I2C multiplexer. 


I am currently trying using the following commands. 


# define HPS_I2C_CONTROL ( 0x00080000 ) 


alt_setbits_word( ( virtual_base + ( ( uint32_t )( ALT_GPIO1_SWPORTA_DDR_ADDR ) & ( uint32_t )( HW_REGS_MASK ) ) ), HPS_I2C_CONTROL ); //output 

alt_clrbits_word( ( virtual_base + ( ( uint32_t )( ALT_GPIO1_SWPORTA_DR_ADDR ) & ( uint32_t )( HW_REGS_MASK ) ) ), HPS_I2C_CONTROL ); 



Yet the LED I have assigned to HPS_I2C_CONTROL indicates it is still active.
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Honored Contributor II

That's exactly the same code as I used and it worked for me. I presume you're setting virtual_base correctly.... ? 


if( ( fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) ) ) == -1 ) { 

printf( "ERROR: could not open \"/dev/mem\"...\n" ); 

return( 1 ); 


virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, HW_REGS_BASE ); 

if( virtual_base == MAP_FAILED ) { 

printf( "ERROR: mmap() failed...\n" ); 

close( fd ); 

return( 1 ); 

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Honored Contributor II

Oh yes, I have the virtual base set up and it successfully maps. 

Also when reading back the GPIO48(see following instruction), I do see that it's cleared. 


hps_gpio = alt_read_word(( virtual_base + ( ( uint32_t )( ALT_GPIO1_SWPORTA_DR_ADDR ) & ( uint32_t )( HW_REGS_MASK ) ) )); 



However, the LED I've assigned to it does not deactivate. 


I'm wondering if you were using Altera University's audio core to interface with the mic. It may be that a few settings on my HPS are not correctly setup.
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Honored Contributor II

I realized that my problem was actually due to a missing clock connection in my Qsys. the clock output of Altera's PLL needs to be exported and linked with AUD_XCK.

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