Syntax in the instantiation of a component

[OMaga]

I'm utilizing a peer's program for counting coincidences of photons between different sources. There are a few components that we can call "XXXX" for example. The instantiation of these components are as follows:

X0 : XXXX

X1 : XXXX

X2 : XXXX

and so on.

When I try to simulate the circuit with modelsim, I receive a warning that each instance of instantiation is not bound (code vsim-3473). I believe the reason I receive this warning because the instantiation does not explicitly match the component, so modelsim doesn't recognize that the two relate. How do I fix this? Can I simply remove the X0, X1, X2, etc... or are they necessary to the program? each instantiation is correlated to a different input, so I feel removing them might mess it up?

Very new to vdhl, so no answer is too simple. Thanks in advance!

[AnandRaj_S_Intel]

Hi,

Check port or generic are matching between instantiation and component.

Compile all component file in modelsim instead of compiling only top file.

If possible share the project and modelsim transcript.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand

[OMaga]

There are no generic ports in this file, and all component ports have an instantiated port map, though the signal names don't match exactly. For example, here's the LCELL component and its instantiation:

COMPONENT LCELL PORT ( a_in : IN STD_LOGIC; a_out : OUT STD_LOGIC); END COMPONENT;   -- This creates, using iteration, a chain of LCELL buffers for each A, B, C, D signal, -- which act to delay the signals. LCA_1: LCELL PORT MAP(a_in=> A, a_out=>A_internal(0));   Gen_delay_A : FOR i in 0 to 23 GENERATE LC : LCELL PORT MAP(a_in => A_internal(i), a_out => A_internal(i+1)); END GENERATE;   LCB_1: LCELL PORT MAP(a_in=> B, a_out=>B_internal(0));   Gen_delay_B : FOR i in 0 to 23 GENERATE LC : LCELL PORT MAP(a_in => B_internal(i), a_out => B_internal(i+1)); END GENERATE; LCC_1: LCELL PORT MAP(a_in=> C, a_out => C_internal(0));   Gen_delay_C : FOR i in 0 to 23 GENERATE LC : LCELL PORT MAP(a_in => C_internal(i), a_out => C_internal(i+1)); END GENERATE; LCD_1: LCELL PORT MAP(a_in=> D, a_out => D_internal(0));   Gen_delay_D : FOR i in 0 to 23 GENERATE LC : LCELL PORT MAP(a_in => D_internal(i), a_out => D_internal(i+1)); END GENERATE;

As for the component files, whenever I add a file to the project, the only folder it allows me to add it to is the "Top Level" folder, I don't know if that's significant.

The attached file is the (actual) top level code. Thanks again.

[AnandRaj_S_Intel]

Hi @OMaga​ ,

We have compile all the files, which are used in top level file.

Can you attach complete project?

Regards

Anand

[OMaga]

All files in zipped folder.

[OMaga]

Update, I noticed that there was no subfile for the LCELL component, so I've created one that is essentially an and gate.

LIBRARY ieee; USE ieee.std_logic_1164.all;   ENTITY LCELL IS PORT ( a_in : IN STD_LOGIC; a_out : OUT STD_LOGIC ); END LCELL;   ARCHITECTURE Behavior OF LCELL IS SIGNAL delayedpulse: STD_LOGIC; SIGNAL KEY: STD_LOGIC;   BEGIN KEY <= '1'; delayedpulse <= a_in AND KEY; a_out <= delayedpulse; END Behavior;

I added this to the project, however, I still receive the "component instance LCELL not bound" error

[AnandRaj_S_Intel · Accepted solution]

​Hi ,

Sorry for the late reply,

For Modelsim you have to Load ALTERA_MF library.

vsim -L altera_mf -L work rs232coincidencecounter

Which Should remove the ** Warning: (vsim-3473) Component instance "LC : LCELL" is not bound.

Attached the transcript.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand