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this is the errror message i had:

Error (10822): HDL error at triangular_carrier.vhd(21): couldn't implement registers for assignments on this clock edge

this is my code:

entity triangular_carrier is

architecture Behavioral of triangular_carrier is

signal x,y:INTEGER:=0;

begin

process(clk,Ts)

begin

case x is

when 0 =>if (clk'event and clk='1') then <---- there is my error occured

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

end if;

when 1 =>if (clk'event and clk='1') then

if y/=0then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

end if ;

end if;

when others=>null;

end case;

end process;

end Behavioral;

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If you wanted to build a sequential case statement in VHDL, the clock event has to put outside of case. Check an example of state machine https://www.intel.com/content/www/us/en/programmable/quartushelp/15.0/mergedProjects/hdl/vhdl/vhdl_pro_state_machines.htm. To compile it, revise the coding as follow:

if (clk'event and clk='1') then

case x is

when 0 => ---- there is my error occured

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

end if;

when 1 =>

if y/=0then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

.............

end if;

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i revise as you teach me

but it appear another error message as showm below

Error (10500): VHDL syntax error at triangular_carrier.vhd(33) near text "process"; expecting "if"

there is my code as i revised :

architecture Behavioral of triangular_carrier is

signal x,y:INTEGER:=0;

begin

process(clk,Ts)

begin

if (clk'event and clk='1') then

case x is

when 0 =>

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

when 1 =>

if y/=0 then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

end if ;

when others=>null;

end case;

end process;

end Behavioral;

would you tell me where am i wrong

thank you so much

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or can i change the code like this

is this same meaning of my code?

architecture Behavioral of triangular_carrier is

signal x,y:INTEGER:=0;

begin

process(clk,Ts)

begin

case x is

when 0 =>if (clk='1') then

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

end if;

when 1 =>if (clk='1') then

if y/=0 then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

end if ;

end if;

when others=>null;

end case;

end process;

end Behavioral;

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