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Altera_Forum
Honored Contributor I
1,048 Views

UP2 board CPLD misbehaving

Hi everyone, 

 

I'm currently using the UP2 dev board along with the free edition of Quartus II web edition software. This has limited me to using the CLPD device (EMP7128SLC84-7) though my code will likely be moved onto the FLEX FPGA at some point. 

 

I'm having trouble with the following code which i retireved from this website: (0 post count, can't post links yet) 

 

entity c1hz is port( clk:in bit; clkout:out bit); end c1hz; architecture behavior of c1hz is begin process(clk) variable cnt : integer range 0 to 12587500; begin if(clk'event and clk='1') then if(cnt=12587500)then cnt:=0; clkout<='1'; else cnt := cnt+1; clkout<='0'; end if; end if; end process; end behavior; I specify using the pin planner that "clk" is pin 83 (the crystal input), and the "clkout" is pin 60 (b of digit 1). these are the only pins specified by me. 

 

The problem is that when the code runs, b does not flash at all. it appears that the output is at c of digit 1, and a of digit 1 also flashes at twice the rate of c. I'm unable to figure out why this is happening. 

 

I do get 3 warnings after a compile: 

 

--- Quote Start ---  

Warning: Using design file c1hz.vhd, which is not specified as a design file for the currnet project, but contains definitions for 2 design units and 1 entities in project 

Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family 

Warning: Found pins functioning as undefined clocks and/or memory enables 

--- Quote End ---  

 

 

Any help in solving this problem would be appreaciated, 

Thanks for your time, 

zammy
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5 Replies
Altera_Forum
Honored Contributor I
19 Views

You surely won't see a LED driven by clkout flashing, because it's only active for one clock cycle. But the warning reveals, that c1hz isn't your design top entity, so it's not clear at all, how the c1hz ports are wired.

Altera_Forum
Honored Contributor I
19 Views

 

--- Quote Start ---  

You surely won't see a LED driven by clkout flashing, because it's only active for one clock cycle. But the warning reveals, that c1hz isn't your design top entity, so it's not clear at all, how the c1hz ports are wired. 

--- Quote End ---  

 

 

Thanks for your reply FvM! 

 

i do see your point about a flashing led, in order to make it flash, would i have to change the 2nd if statement condition to if (cnt < '12587500') rather than if (cnt = '12587500')? 

 

i'm not sure why c1hz isn't my top entity, all i did was create a new project and a new vhdl file and pasted the code in, and set the pins i wanted to use.
Altera_Forum
Honored Contributor I
19 Views

 

--- Quote Start ---  

i'm not sure why c1hz isn't my top entity 

--- Quote End ---  

 

When you set a design file as top entity, it's automaticly included in the project file list. Then you won't get the said warning "Using design file c1hz.vhd, which is not specified as a design file". Thus I assumed, you have a different top entity. But you see this clearly in the design hierarchy view.
Altera_Forum
Honored Contributor I
19 Views

 

--- Quote Start ---  

When you set a design file as top entity, it's automaticly included in the project file list. Then you won't get the said warning "Using design file c1hz.vhd, which is not specified as a design file". Thus I assumed, you have a different top entity. But you see this clearly in the design hierarchy view. 

--- Quote End ---  

 

 

ah.. i believe i named my project something else, is it the entity not matching the project name that throws this error?
Altera_Forum
Honored Contributor I
19 Views

OK, i managed to throw out a 1Hz blinking led by writing my own code and i understand it fully, but the original problem of other LED's flashing on the board is still occuring. I've only specified one output pin in my code, yet the neighbour pins are also being toggled it seems. 

 

Is this simply a result of the Fitter + Router using logic elements that are nearby physically, and because i'm not using the pins it is ok to "mess" with them? If i were to use those pins, would it re-route the noisy parts to other parts of the CLPD? 

 

 

Also, i'm still not quite sure what the different pin icons of the Pin planner represent. Is there a reference chart or a primer somewhere so that i can read up on this?
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