Intel® FPGA University Program
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University Core, I2C, and Me

Honored Contributor II

I've seem to hit a brick wall designing my own I2C module in Verilog for the on board peripherals that accompany the DE2-115 board. So I decided to give the University Program IP Cores a try. 


I have a project this term and wanted to use the D5M camera and the Wolfson WM8731 chip on the board for some sound. I tried to use the Audio & Video Config as well as the Audio core from the University program but they are not working (the LCD Character core works fine). 


I've checked the traces with my logic analyzer and every time the cores send out commands over the I2C channel the devices (D5M and WM8731) return NACK acknowledgements. Oddly enough, the very first command to the D5M (the address) returns an ACK, but all commands thereafter return NACK; while the WM8731 returns an NACK for every command. 


I loaded the Terasic (or Altera, I'm unsure) D5M demonstration and also looked at the trace for that. This demonstration seems to be working fine and the D5M acknowledges every command sent.  


Now, this leads me to believe there must be an issue with either the cores (unlikely, but that D5M ACK/NACK is odd) or my circuit. Maybe I'm not implementing bidirectional lines correctly but I'm just setting the output of the core (I2C_SCLK and I2C_SDAT) to some internal wires. Then, I'm setting the wires to the device (I tried one at a time just to be sure), and also to an EX_IO pin (this is how I see the trace).  


I'm very confused because the problem with my personal core is also no device acknowledgements although the traces look good. Below is the connection of the data line. Any advice would be awesome. Thanks everyone, and also if you want trace pictures or full source code just send me a message I just don't want to clutter this post. 


This code is the relevant portions, if the multiple assignment of wires don't make sense, it does to me in the overall circuit design (and its on-the-fly debugging). 


// Wires 

wire sda; 

wire scl; 

wire d5m_scl; 

wire d5m_sda; 


assign sda = d5m_sda; 

assign scl = d5m_scl; 


// Inside NIOS module 

niosCPU cpu0 



/* D5M (Altera IP) */ 






// Outputs to the world 

output [6:0] EX_IO; 


assign EX_IO[0] = sda; 

assign EX_IO[1] = scl; 



Thanks again.
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