Intel® FPGA University Program
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Using Triple Speed Ethernet on DE2-115 Board Infintie Reset Loop

Altera_Forum
Honored Contributor II
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I am attempting to run Altera's Using Triple Speed Ethernet on the DE2-115 board but I have run into a problem. I have compiled and downloaded the hardware successfully with Quartus II 13.1 and 13.0sp1 but have run into a problem running the provided C file in the Eclipse environment. The while loop in line 94 that waits for the 2nd PHY to be reset and should exit when the PHY sets the reset bit low. The problem is that this never happens and the loop runs indefinitely.  

 

Tutorial link: http://www.altera.com/education/univ/materials/boards/de2-115/unv-de2-115-board.html
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I am attempting to run Altera's Using Triple Speed Ethernet on the DE2-115 board but I have run into a problem. I have compiled and downloaded the hardware successfully with Quartus II 13.1 and 13.0sp1 but have run into a problem running the provided C file in the Eclipse environment. The while loop in line 94 that waits for the 2nd PHY to be reset and should exit when the PHY sets the reset bit low. The problem is that this never happens and the loop runs indefinitely.  

 

Tutorial link: http://www.altera.com/education/univ/materials/boards/de2-115/unv-de2-115-board.html 

--- Quote End ---  

 

 

I met the same problem。Can anybody give some advice?
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