VHDL code for JK flip-flop issue

[Wcheekei]

Hi,

I'm having issue trying to understand the code generated by the software Intel Quartus Prime. The JK flip-flop block used has an IF-ELSE statement that conflicts with each other. The SYNTHESIZED_WIRE_2 are checked for '0' twice and assigned with different values. That would mean the second statement will never be executed. Any ideas on what it means and how it works?

[FvM · Accepted solution]

Hello,
synthesized code is often not well readable. The strange SYNTHESIZED_WIRE_2 coding is produced by connecting set and reset inputs together in your schematic input. Nevertheless it's logically correct.

Most recent FPGA families don't support simultaneous usage of asynchronous set and reset, you should avoid it in code intended for FPGA synthesis.

[RichardTanSY_Intel]

Yes, he is right. To add-on, asynchronous set and reset signals are not synchronized to the clock and can introduce timing hazards and metastability issues. The simultaneous use of asynchronous set and reset signals in a flip-flop can lead to race conditions, data instability, and unpredictable behavior, making it difficult to meet timing requirements and ensure reliable operation.

You may checkout this document for further details.

https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/asynchronous-design-hazards.html

We recommend that users to follow the Synchronous FPGA Design Practices.

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey

[RichardTanSY_Intel]

Thank you for acknowledging the solution provided. I'm glad to hear that your question has been addressed. Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Thank you and have a great day!

Best Regards,

Richard Tan