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VWF simulation stuck

Altera_Forum
Honored Contributor II
844 Views

Hello,  

 

I'm facing a little problem with simulation. I've built a system which takes stream from TRDB-D5M camera converts to grayscale, performs edge detection and sends it to VGA controller. 

All this is done in Qsys with university program components.  

The stream is also stored on external SDRAM on DE0-nano board. 

The SDRAM controller does not create DRAM_CLK signal when exported, which should be 50MHz clock to SDRAM chip on board. So I export Special SDRAM clock signal from "Clock signals for DE-series Board Peripherals". And connect it to R4 pin (according to manual).  

Then I'm trying to perform functional simulation with university program VWF. Ant it stucks. Even all quartus II software is stuck. But when I do not use this DRAM_CLK pin, everything is fine, I mean with simulation. But not fine with memory there is no data because lack of clock signal I think. 

 

Does anyone have faced with this or similar problem and could assist me? 

 

Thank You. 

 

P.S. I'm using Quartus II web edition 13.1 

 

Regards.
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