Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
1228 Discussions

When I am running <boardtest> problem with the terasic DE10 CycloneV SOC board with Quartus 19.1 Prime Standard using OpenCL, I am getting the following error. boardtest.log is uploaded.

PVeli
Beginner
‎01-24-2020 05:48 AM
1,128 Views

2020.01.24.19:58:38 Error: pll_rom: Failed to find module system_acl_iface_acl_kernel_clk_pll_rom

2020.01.24.19:58:38 Info: pll_rom: "acl_kernel_clk" instantiated altera_avalon_onchip_memory2 "pll_rom"

2020.01.24.19:58:38 Error: Generation stopped, 72 or more modules remaining

2020.01.24.19:58:38 Info: system: Done "system" with 65 modules, 213 files

 

boardtest.log
0 Kudos

Link Copied

1 Reply
FawazJ_Altera
Employee
‎02-04-2020 07:57 AM
877 Views

Hello,

Is it DE10 Nano or DE10 Standard board?

Did you recompile the design using the same version supported by Terasic?

 

Thank you

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.