When I am running <boardtest> problem with the terasic DE10 CycloneV SOC board with Quartus 19.1 Prime Standard using OpenCL, I am getting the following error. boardtest.log is uploaded.

[PVeli]

2020.01.24.19:58:38 Error: pll_rom: Failed to find module system_acl_iface_acl_kernel_clk_pll_rom

2020.01.24.19:58:38 Info: pll_rom: "acl_kernel_clk" instantiated altera_avalon_onchip_memory2 "pll_rom"

2020.01.24.19:58:38 Error: Generation stopped, 72 or more modules remaining

2020.01.24.19:58:38 Info: system: Done "system" with 65 modules, 213 files

[Fawaz_Al-Jubori]

Hello,

Is it DE10 Nano or DE10 Standard board?

Did you recompile the design using the same version supported by Terasic?

Thank you