helloi'm doing a university project that involves the back lights of a ford thunderbird. i have three separate state machines: one for left & right turns one for break, break+left turn, & break+right turn one for break, hazards, & break+hazards individually, they all work the way they are supposed to on the board (cyclone ii). however i am having trouble combining each state machine to a single bdf file. i tried combining the bus wires to the same output (the lights) but there is an error when compiling. how do i get them all to the same outputs? i'm using 9.0 build 235 here is a layout of how i have the bdf so far: thank you for your help
How do you combine them? Do you simply wire them together? Then , your error is surely something like "Output with multiple drivers"You must use OR gates to combine those bus wires, if they are active high. If active low, use AND gates.
For example all your 3 blocks are supposed to control the r output.You can't connect them in parallel because each line would drive a defined state, high or low, so there would be conflict. You must use a OR3 gate: this is an OR gate with 3 inputs which will receive r from your 3 blocks, while the ORed output will drive the fpga pin, namely the right light. Same for other r lines and same for other signals: use OR3 or OR2 depending how many sources you need to mix.
Just to make sure I understand what you're saying:I need to wire the r[3..0] from each state machine to an OR3/2 gate that I use and then wire that to the r...r outputs? Is there anyway you can show me a mock-up with one of the outputs?
Thank you so much. I just have one more issue.Is there a way to like set up the gates so if the hazards are activated in the specific state machine, regardless if i turn on the turn switches, the hazards will stay?
If I understand correctly what you mean, you need to gate the turn signals before the state machine.Say you rename iL the signal coming from turn left input pin and sL the signal to the state machine. In your current design they are the same. You must gate iL with the h signal, using an AND and a NOT gate. sL = iL AND (NOT h)