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Altera_Forum
Honored Contributor I
859 Views

hey guys homework help

i have the following program which makes a finite state machine.it compiles but doesnt simulate what could be wrong?this is the code i came up with for he question 

This is an exercise in using finite state machines. 

Part I 

We wish to implement a finite state machine (FSM) that recognizes two specific sequences of applied input symbols, 

namely four consecutive 1s or four consecutive 0s. There is an input w and an output z. Whenever w = 1 or 

w = 0 for four consecutive clock pulses the value of z has to be 1; otherwise, z = 0. Overlapping sequences are 

allowed, so that if w = 1 for five consecutive clock pulses the output z will be equal to 1 after the fourth and fifth 

pulses. Figure 1 illustrates the required relationship between w and z. 

 

the code 

module part1a(clk, in, reset, out); 

 

input clk, in, reset; 

output [8:0] out; 

 

reg [8:0] out; 

reg [8:0] state; 

reg count = 0; 

 

parameter zero=0, one=1, two=2, three=3,four=4,five=5,six=6,seven=7,eight=8; 

 

always @(state)  

begin 

case (state) 

zero: 

out = 9'b000000001; 

one: 

out = 9'b000000010; 

two: 

out = 9'b000000100; 

three: 

out = 9'b000001000; 

four: 

out = 9'b000010000; 

five: 

out = 9'b000100000; 

six: 

out = 9'b001000000; 

seven: 

out = 9'b010000000; 

eight: 

out = 9'b100000000; 

 

 

default: 

out = 9'b000000000; 

endcase 

end 

 

always @(posedge clk or posedge reset) 

begin 

if (reset) 

begin 

state = zero; 

count = 0; 

end 

else if(count==0)  

begin 

case (state) 

zero:  

if(in) 

begin 

state = one; 

count <= 1; 

end 

else 

begin 

state = two; 

count <= 1; 

end 

endcase 

end  

else if(count==1) 

begin 

case (state) 

one: 

if (in) 

begin 

state = three; 

count <= 1; 

end 

else 

begin 

state = two; 

count <= 1; 

end 

two: 

if(!in) 

begin 

state = four; 

count <= 2; 

end 

else 

begin 

state= one; 

count = 1; 

end 

endcase 

end  

else if (count==2) 

begin 

case (state) 

three: 

if(in) 

begin 

state = five; 

count = 3; 

end 

else 

begin 

state = two; 

count = 1; 

end 

four: 

if(!in) 

begin 

state = six; 

count = 3; 

end 

else 

begin 

state = one; 

count = 1; 

end 

endcase 

end 

else if(count==3) 

begin 

case (state) 

five:  

if(in) 

begin 

state = seven; 

count = 4; 

end 

else 

begin 

state = two; 

count=1; 

end 

six: 

if(!in) 

begin 

state = eight; 

count = 4; 

end  

else 

begin 

state = one; 

count = 1; 

end 

endcase 

end  

else if(count==4) 

begin 

case(state) 

seven: 

if(in) 

begin 

state = seven; 

end 

else 

begin 

state = two; 

count = 1; 

end 

eight: 

if(!in) 

begin 

state = eight; 

end 

else 

begin 

state = one; 

count <= 1;  

end 

endcase 

end 

else 

begin 

state = zero; 

count <= 0; 

end 

end 

 

endmodule
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2 Replies
Altera_Forum
Honored Contributor I
27 Views

If I understood correctly what you want to obtain, your code is a mess. 

In particular: Why that 9bit register for a single output? 

You can do it with this much simpler code, involving a simple shift register. 

 

module part1a(clk, in, reset, out); input clk, in, reset; output out; reg out; reg shifter; always @(posedge clk or posedge reset) begin if (reset) begin out <= 1'b0; shifter <= 4'b0101; end else begin if (shifter == 4'b0000) out <= 1'b0; else if (shifter == 4'b1111) out <= 1'b1; shifter <= { shifter , in }; end end  

This is only sort of template; check syntax and operation. 

 

Regards
Altera_Forum
Honored Contributor I
27 Views

im new to verilog and its really confusing,thanks for the help, really appreciated