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"Hook up" guide for Altera IP cores?



I am an FPGA beginner and recently bought the DE10 Standard board.

My university does teach FPGA topics but for the electronics engineering students, and I am studying computer science, so please forgive my probably dull question.

Straight to the point. I would like to use the onboard audio chip to analyse incoming audio.

I have configured the audio input IP to supply 16 bit output from ADC (streaming, as I am going to use FPGA for this), with 48kHz sampling rate. For this i used the AV config IP.

There is one thing though - I have no idea how to connect both of the IPs. For reference, I provide a picture of what I have now:


Now, I guess i got the output right. But the input - no idea. Most of the outputs of AudioConfig are not even present as input in AudioInput IP, or the audio chip that lies underneath it. I know the physical audio chip is configured via I2C, but I see no I2C inputs in the AudioInput IP.

Also, I found no reference in the documentation provided by altera as to what "reference", "readdata", "writedata", "read", "write", "byteenable" and "address" pins mean - such names are nowhere to be found in the documentation.

So, Is there a hookup guide for these IP's that I can read to know what goes where?

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As I understand it, you have some inquiries related to some audio IPs. To ensure we are on the same page, would you mind to share with me further on the specific AudioClock, AudioConfig and AudioInput IPs that you are using? Some reference to the IP Catalog would be helpful. Also, please share with me which Quartus version are you using?

This will be helpful for me to help identifying the right person to further assist you.

Thank you.

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As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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