Intel® FPGA University Program
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sampling rate conversion project

Honored Contributor II

hi everyone, 


i am an electrical engineering student and i am currently working on a project called "verilog design of an fpga based sampling rate converter". i m using altera de1 board as an fpga device. 


main task is to design interpolation and decimation filter. need to do testing on the board for a conversion of 8 KHz to 32 KHz 


i would like some idea as to how can i get started on this project. 


thank u all, 

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Honored Contributor II

A popular method with hdl based interpolator/decimator is to use one single FIR filter to implement the conversion. 


Any FIR will do. The FIR should cut off the first image.  

for example to interpolate 8KHz to 32KHz, use one single filter that cuts off at 1/4 band or so. divide your filter into 4 polyphases: 


p1 : 0,4,8...) 

p2 : 1,5,9...) 

p3 : 2,6,10,...) 

p4 : 3,7,11,...) 


then produce an output per each polyphase subfilter. advance input once per 4 cycles. The whole filter can run on 32KHz but input advanced on 8Khz. 


If your interpolation is by 2(or its multiples) then halfband (or lower order) filter will do. The halfband approach contains useful zeros and so does not need polyphase implementation.  


You can use altera fir compiler or DSP builder to do it for you if you are not supposed to do coding by hand.
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