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stratix 10dx PCIe gold finger recognition

EastGun-A
Novice
1,289 Views

Hello, thank you for always helping me.

I use 'LSPCI' to check the PCIE device, but the PCIE of the FPGA is not recognized.

While designing the FPGA logic, slack comes out as a negative value.

Could that be the problem?

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wchiah
Employee
1,164 Views

Hi,


I am not sure what you had modified.

But I suggest you to look back the design, ensure all pin is connected in what the IP suggested.


Regards,

Wincent_Intel


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wchiah
Employee
1,275 Views

Hi,


As long as the slot of the Host PC can support the desired PCie gen speed,

then it should be able to at least detect the FPGA’s PCIe interface (provided it can link up correctly).



Did you try to program any .sof file yet ?

If not I suggest you to try to generate one from the Quartus "IP catalog"

Also, You may try the same with different PC/server/slots to isolate if there is any dependency, and then you can also compare the BIOS setting for any difference.


Regards,

Wincent_Intel


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EastGun-A
Novice
1,269 Views

I changed the sof file to pof and proceeded with programming.
Well, while modifying the pcie example, slack got -88, so I wonder if this is why it is not recognized.
Although the link up has been completed, I have confirmed that the completion TLP of the configuration read does not return, so I wonder if it is a problem caused by slack (setup/hold time violation).

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wchiah
Employee
1,247 Views

Hi, 

  1. Do the error happen while you program the .sof file as well ?
  2. Do the TLP configuration read able to complete without modifiying anything ?
  3. What is the LTSSM status ? is it in L0 stage ?
  4. Can you show the printscreen error of slack -88 ?

Regards

Wincent_Intel

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EastGun-A
Novice
1,225 Views

Well, I couldn't attach the file now (I haven't received the detailed LTSSM status and file yet), but TLP communicated normally before the fix.
The sof file was also programmed normally. (both before and after TLP correction)

 

thank you always.

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wchiah
Employee
1,210 Views

Hi,


 but TLP communicated normally before the fix.

The sof file was also programmed normally. (both before and after TLP correction)


>> do you means the TLP and sof file able to run in good condition before you modifiying the design example ?


Regards,

Wincent_Intel


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EastGun-A
Novice
1,198 Views

yeah, it's right!

 

'lspci' figured out the "PCIe device" before modifying.

It is not recognized  after modification. (slack is changed positive 0.03 to negative -88) 
I programmed the sof file in the same process.

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wchiah
Employee
1,165 Views

Hi,


I am not sure what you had modified.

But I suggest you to look back the design, ensure all pin is connected in what the IP suggested.


Regards,

Wincent_Intel


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wchiah
Employee
1,141 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
1,055 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

 

Regards,

Wincent_Intel


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