Intel® FPGA University Program
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up_ip_core help me!

Altera_Forum
Honored Contributor II
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Hi! 

 

I have a DE2-70 board with Quartus 9.0 + nios2 IDE 9.0. I'd like to design a nios2 cored system with up_ip_core 9.0. works on 100MHz and that must be control all board's component resources (vga, lcd, ethernet etc.). So all components on board can be controlled with a suitable software running on nios2 unless changing the FPGA hardware structure. What must the clock sources be for all components or how can I set the suitable clock sources for each component and pipeline bridge ? Do you have any example of this or source matterial.?  

 

thanks for your helps.
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Altera_Forum
Honored Contributor II
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As far as I know there is no single precooked design that illustrates all of the features that you mentioned. The best starting point for the DE2-70 is the accompanying cd-rom (http://www.terasic.com/downloads/cd-rom/de2_70/). It has a number of sample projects in source code that illustrate the use of most of the peripherals of the DE2-70 system.

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