Any support for Prescott?

[dave_frank]

Steve
Will next Fortran support the Intel "Prescott" chip
which is rumored to have a 64-bit instruction set
and MAY be released BEFORE your compiler.

[TimP]

The 8.0 compilers support the Prescott new instructions, likely to be called SSE3. There is no support for extended addressing.

[Steven_L_Intel1]

Tim is correct - Intel Visual Fortran will have an option to specify the Prescott processor, which will enable generation of SSE3 instructions (the "SSE3" name was already made public.) The documentation will refer to "Intel processor code name Prescott", as we haven't been told a distinguishing name we can use.

The 8.0 compilers will also have a new option for Pentium-M (Banias) - previously, we said to use the Pentium 4 setting.

Steve

[durisinm]

I'm currently working on a CVF 6.6B program to be run on computers with a combination of Pentium 4 and M CPUs. I'm using the /architecture and /tune options for Pentium 4. How would the resulting .exe file differ from ones built with IVF for just Pentium 4 or just Pentium M?

Mike

[TimP]

As CVF doesn't generate SSE code, the effect of those switches might resemble 'IFL /Qxi /G7' (generate P-II compatible code with scheduling and choice of instructions adjusted to favor P4). The next round of compilers may eliminate the P-II switch, so that it will not be possible to use conditional move instructions without SSE.
The /QxW switch generates code with SSE and SSE2 instructions, including parallel instructions, and requires an SSE2 CPU. It avoids as much as possible the use of integer shift and multiply instructions, which have been slow on P4. The Pentium M switch would use those instructions more frequently, in the interest of generating more compact code.

[Steven_L_Intel1]

CVF is a little better than that. It knows how to generate SSE data prefetch instructions and also uses models of the memory subsystem for PIII and P4 in its array transformations.

Steve

[TimP]

Steve:

Steve: That's interesting; I've never seen IFL/ifc generate software prefetch instructions with the P4 switches, even where they might have an advantage. If CVF knows where the P4 family processors want a prefetch, could future compilers take advantage of that?

Prescott is intended to alleviate the performance penalty for redundant software prefetch as seen up to now on P4. One aspect, a possible down side, of this, is that it should no longer be possible to give hardware prefetch a head start by issuing software prefetch prior to a loop.

[Steven_L_Intel1]

If I recall correctly, we did see some improvement in CVF by generating some prefetches for P4. While CVF doesn't generate SSE2 instructions, we had to add a P4 optimization mode to not get worse performance than a P3 (due to the prefetches that the P4 doesn't like.)

Steve