MMX EMMS warning

[ggveldkamp2]

When compiling some source file I get the following warning:

Warning: MMX instructions are followed by a call without first having seen an EMMS instruction in file C:localV52sourcesplib_camschrijfrep.f, line 4497, column 12

I am using /O2 /QxK flags for optimization. Could this cause problems for the program? Can this warning be avoided, maybe by changes to the source?

Thanks,

Guido

[TimP]

One way to avoid it would be to use one of the options for P4 or later CPUs (SSE2 options -QxW ..). It has been some years since any manufacturer made a CPU which would not support -QxW. If this warning comes from an obsolete compiler, an upgrade could be worth while.

I have heard that CPUs which support SSE2 avoid thesharing ofMMX and x87 registers which prompted this warning, but I can't find quickly a reference to verify it. You can easily find Google references which explain that the first MMX CPUs used the same registers for MMX and floating point, and could not safelypass fromMMX to floating point instructions without issuing the EMMS. All these issuesseem mainly historical.

[ggveldkamp2]

The compiler is IVF 9.1.028. Our software is running on many different machines so I am a bit conservative with the optimizations. An Athlon XP that is a few years old does not support SSE2.
I wonder why the compiler doesn't insert the EMMS instruction itself. Maybe because it doesn't know if the called function is using floating point instructions (in this case I think it is not and the warning is probably harmless).
Would it be possible to insert an EMMS instruction by some function call or compiler directive?

[Steven_L_Intel1]

This sounds as if it may be a compiler bug. Please submit a test case to Intel Premier Support.

[ggveldkamp2]

I submitted a test case to Intel Premier Support.

[TimP]

As you say, if the function does not use floating point, you would not have a problem, even on a P-III.If ituses only SSE single precision (-QxK), you might escape any problem. The 32-bit Athlon, even though it does not support SSE2, may already keep the MMX and x87 registers separate, so there would be no problem, even with double precision floating point.