Now that the site is accepting replies (grudgingly): the considerations depend on your choice of architecture. On P4/Netburst systems, most important is to have the vectors start at 16-byte-aligned addresses. Then you can begin to deal with making your loop lengths a multiple of 8, in case they involve unrolling by that factor. Beyond that, you could search for the greatest length which does not begin to incur more L2 cache misses (smaller with HyperThreading in use). Look for data placement which reduces cache mapping conflicts (e.g. 64k aliasing); this probably contradicts your idea about relation to cache length.
