Sig Diff results from same settings between DLL and EXE versions?

[lklawrie]

I have a rather large code and one of our users noticed (he uses and distributes) big differences in results between the DLL and our regular version. In trying to track this down, I too am noticing differences between the two. I'm using the Arch32 compiler setting because another tester can't seem to run other settings on his AMD processor (am currently trying to find out more about which AMD processor this is.

Anyway, here are my pertinent command line settings for both compiler and linker. Any ideas?
Compiler:
DLL: /nologo /debug:minimal /assume:buffered_io /arch:IA32 /fpscomp:nolibs /Qzero /fpe:0 /module:"Release\" /object:"Release\" /traceback /libs:static /threads /4Yportlib /c
EXE: /nologo /debug:minimal /assume:buffered_io /arch:IA32 /fpscomp:nolibs /Qzero /fpe:0 /module:"Release\" /object:"Release\" /traceback /libs:static /threads /4Yportlib /c

Link:
DLL: /OUT:"Release\EnergyPlusDLL.dll" /NOLOGO /MANIFEST /MANIFESTFILE:"D:\EPPgm\EnergyPlusDLL\Release\EnergyPlusDLL.dll.intermediate.manifest" /SUBSYSTEM:WINDOWS /IMPLIB:"D:\EPPgm\EnergyPlusDLL\Release\EnergyPlusDLL.lib" /DLL
EXE: /OUT:"Release\EnergyPlus.exe" /INCREMENTAL:NO /NOLOGO /MANIFEST /MANIFESTFILE:"D:\EPPgm\IVF\EnergyPlus\Release\EnergyPlus.exe.intermediate.manifest" /SUBSYSTEM:CONSOLE /IMPLIB:"D:\EPPgm\IVF\EnergyPlus\Release\EnergyPlus.lib"

Linda

[Steven_L_Intel1]

My first guess would be a reference to an uninitialized variable - memory layout will change depending on DLL or EXE.

As for the AMD processor - the default is that execution requires a processor that supports SSE2 instructions. Many older AMD processors don't support SSE2.

[Paul_Curtis]

Quoting - Steve Lionel (Intel)

...As for the AMD processor - the default is that execution requires a processor that supports SSE2 instructions. Many older AMD processors don't support SSE2.

Here is the processor capabilities list from Wikipedia:

CPUs supporting SSE2

* AMD K8-based CPUs (Athlon 64, Sempron 64, Turion 64, etc)
* AMD Phenom CPUs
* Intel NetBurst-based CPUs (Pentium 4, Xeon, Celeron, Celeron D, etc)
* Intel Pentium M and Celeron M
* Intel Core-based CPUs (Core Duo, Core Solo, etc)
* Intel Core 2-based CPUs (Core 2 Duo, Core 2 Quad, etc)
* Intel Core i7
* Intel Atom
* Transmeta Efficeon
* VIA C7
* VIA Nano

Notable IA-32 CPUs not supporting SSE2

The following CPUs implemented IA-32 after SSE2 was developed, but did not implement SSE2:

* AMD CPUs prior to Athlon 64, including all Socket A-based CPUs
* Intel CPUs prior to Pentium 4
* VIA C3
* Transmeta Crusoe

[TimP]

Quoting - Paul Curtis

Here is the processor capabilities list from Wikipedia:

CPUs supporting SSE2

* AMD K8-based CPUs (Athlon 64, Sempron 64, Turion 64, etc)
* AMD Phenom CPUs
* Intel NetBurst-based CPUs (Pentium 4, Xeon, Celeron, Celeron D, etc)
* Intel Pentium M and Celeron M
* Intel Core-based CPUs (Core Duo, Core Solo, etc)
* Intel Core 2-based CPUs (Core 2 Duo, Core 2 Quad, etc)
* Intel Core i7
* Intel Atom
* Transmeta Efficeon
* VIA C7
* VIA Nano

Notable IA-32 CPUs not supporting SSE2

The following CPUs implemented IA-32 after SSE2 was developed, but did not implement SSE2:

* AMD CPUs prior to Athlon 64, including all Socket A-based CPUs
* Intel CPUs prior to Pentium 4
* VIA C3
* Transmeta Crusoe

Turion X2 apparently has full support for SSE2, but the first Turion may not have.
I do remember some P-III CPUs (no SSE2) which came out after P4, but they didn't achieve much popularity.

[lklawrie]

Quoting - Steve Lionel (Intel)

My first guess would be a reference to an uninitialized variable - memory layout will change depending on DLL or EXE.

As for the AMD processor - the default is that execution requires a processor that supports SSE2 instructions. Many older AMD processors don't support SSE2.

Ya, maybe Steve. (check uninit flag didn't flag anything)

Furthermore, removing the arch 32 flag and the DLL and EXE are the same or virtually the same results. (this is over a test suite of some 300 files). A few odd looking diffs but mostly "same".

Linda

[lklawrie]

Extensive testing (compiler switches) reveals this is strictly an Arch32 flag problem. Is this worthy of a small program to illustrate and send it to the support people as a problem? Or I could provide exe and dll to illustrate the two. (along with some test files).

Linda

[Wendy_Doerner__Intel]

Quoting - lklawrie

Extensive testing (compiler switches) reveals this is strictly an Arch32 flag problem. Is this worthy of a small program to illustrate and send it to the support people as a problem? Or I could provide exe and dll to illustrate the two. (along with some test files).

Linda

Linda,

Steve is out for a couple of days, so I am responding. Yes a small test case (you can post it to this forum) would be helpful for us to see if there is a problem with the arch32 switch.

Please include any information about the processors and results you are running. Note that floating point results can vary if you do not use the /fp:precise option (which gives consistency of results by turning off some optimizations).

Wendy