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I have noticed some very signficant numbers in the compile time figures with IF9.
We have a software tool that generates FORTRAN files automatically and these files are compile into a library to form an electrical network matrix simulation. Recently IF9 compatibility has been incorporated with our latest version of the simulator software. Under different setting, some of the timing numbers are quite large and this is having an effect on the overall product performance. Here are some numbers:
Testing with the Intel Fortran V9 compiler versus
the Compaq Fortran V6.6 compiler (previous version):
Input: 255 FORTRAN subroutine files:
CF6 160s standard (/debug:none /optimize:3 /fast)
IF9 1500s standard (/Ob2 /Op and /optimize:2 is defaulted)
IF9 270s customized (/optimize:1 /Op)
IF9 120s customized (/optimize:0 /Op)
There is definitely a concern with the compile speed of the
Intel V9 compiler (it was almost 10 times slower to compile
the .f files produced for a large case with /opt:2).
Is this to be expected, or is there something I am missing here?
We have a software tool that generates FORTRAN files automatically and these files are compile into a library to form an electrical network matrix simulation. Recently IF9 compatibility has been incorporated with our latest version of the simulator software. Under different setting, some of the timing numbers are quite large and this is having an effect on the overall product performance. Here are some numbers:
Testing with the Intel Fortran V9 compiler versus
the Compaq Fortran V6.6 compiler (previous version):
Input: 255 FORTRAN subroutine files:
CF6 160s standard (/debug:none /optimize:3 /fast)
IF9 1500s standard (/Ob2 /Op and /optimize:2 is defaulted)
IF9 270s customized (/optimize:1 /Op)
IF9 120s customized (/optimize:0 /Op)
There is definitely a concern with the compile speed of the
Intel V9 compiler (it was almost 10 times slower to compile
the .f files produced for a large case with /opt:2).
Is this to be expected, or is there something I am missing here?
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"expected"? No. The Intel compiler does more optimizations than CVF and can sometimes be slower, but it is also sometimes faster.
I would recommend that you submit a support request to Intel Premier Support and attach a ZIP file of your project and sources so that we can determine if there is a way we can improve the compile time. I have seen a number of such issues in the past and we are often able to make significant improvements.
I would recommend that you submit a support request to Intel Premier Support and attach a ZIP file of your project and sources so that we can determine if there is a way we can improve the compile time. I have seen a number of such issues in the past and we are often able to make significant improvements.
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Hello,
For very large projects the long compile time can be a problem.
However, there is a nice workaround that can reduce compilation
time, reduce executable size and also slightly increase the performance of your software, please read this thread:
Setting up your makefile or VS.NET solution may take a while, because you have to use Intel VTune to determine how each file should be compiled - but after the job is done, you can sit back, relax and enjoy the fast compilation, becausethe compiler is only spending time optimizing the code that is responsible for most of the CPU time.
Best Regards,
Lars Petter Endresen
Message Edited by lpe@scandpower.no on 12-06-2005 12:25 PM
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Thankyou for your input and the link to a discussion thread, it helps a lot.
At this point we do not yet have any customers using IF9. Since they are all still on previous versions, that buys us some time to experiment with switch settings to optimize the performance for the simulator and post an updated file to new users.
Since the source files are auto-generated by the schematic compiler, the subroutine patterns are very similar and perhaps one optimization function is being overloaded. I will post an update if I find a useful tip.
Thanks,
Craig.
At this point we do not yet have any customers using IF9. Since they are all still on previous versions, that buys us some time to experiment with switch settings to optimize the performance for the simulator and post an updated file to new users.
Since the source files are auto-generated by the schematic compiler, the subroutine patterns are very similar and perhaps one optimization function is being overloaded. I will post an update if I find a useful tip.
Thanks,
Craig.

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