Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
677 Discussions

10M08SAU324I7G SMAP Length Routing constraints

Dhilip
Beginner
455 Views

Hi , 

We are using 10M08SAU324I7G chipset in our design. We are using SMAP interface to Program the FPGA(XCKU5P series) from CPLD.

 

Below are the Pins are used for SMAP interface. In our design, we have routed 15inch traces between FPGA and CPLD due to dense board. For this we have simulated and it pass only "18_RIO_R50C" model. 

Is it possible to configure this "18 RIO R50C" model for the pins listed below?Please advise and share if any guidelines.

 

Dhilip_1-1655063252574.png

 

0 Kudos
2 Replies
Farabi
Employee
424 Views

Hello,


You can confirm this by referring to MAX10 ibis model.

Download link : https://cdrdv2.intel.com/v1/dl/getContent/674923?explicitVersion=true


regards,

Farabi


0 Kudos
Farabi
Employee
424 Views

Hello,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


rgards,

Farabi


0 Kudos
Reply