I believe this issue is a somewhere between High Level Design and the Intel Devcloud environment. If this post is better suited to be asked elsewhere, feel free to let me know.
Below is the error I am a bit stuck on:
terminate called after throwing an instance of 'cl::sycl::runtime_error'
what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY)
Aborted
I have been using the "Hough_Transform_on_FPGAs_Using_oneAPI" jupyter notebook collection as a reference for this process. From what I have read, this error seems to usually be related to trying to run an FPGA bitstream on the wrong type of device. I am fairly certain everything I have done should be aimed an an arria10 device, though I could be wrong. Everything appears to work fine on an emulator or a normal program compilation. I only run into trouble running on the actual FPGA hardware.
This is the command I have been submitting to an fpga_compile node. My understanding is that this should default to be arria10 compatible.
dpcpp -v -fintelfpga -Xshardware main.cpp -o pseudo.fpga
I have tried running this on different fpga_runtime / fpga_runtime:arria10 nodes with no success. Below I am including the section of my code where the error is occurring incase it is helpful, but I do not believe it is currently the cause of my issue. (I might be very wrong though!)
device_queue.submit([&greyscale_buffer, &image_buffer, image, width, height, out](cl::sycl::handler& cgh) {
// A discard_write is a write access that doesn't need to preserve existing memory contents
auto data = greyscale_buffer.get_access<cl::sycl::access::mode::discard_write>(cgh);
auto image_data = image_buffer.get_access<cl::sycl::access::mode::read>(cgh);
// THIS PARALLEL_FOR IS WHERE THE ERROR OCCURS
cgh.parallel_for(cl::sycl::range<1>(width * height), [image_data, out](cl::sycl::id<1> idx) {
// Just commented out code inside currently
});
}).wait();
If there's anyone who could help point me in the right direction it would be much appreciated. Thanks!
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Hi,
pls follow bellow guidance document.
reference:
Thanks,
Unfortunately this does not seem to resolve the issue. I see this documentation states, "the compiler chooses the default FPGA board variant pac_a10 from the intel_a10gx_pac BSP". I connected to an fpga_runtime:arria10 node and ran the following command:
> aocl initialize acl0 pac_a10
aocl initialize: Running initialize from /glob/development-tools/versions/oneapi/2022.2/oneapi/intelfpgadpcpp/2022.1.0/board/intel_a10gx_pac/linux64/libexec
Program succeed.
After doing this, I still run into the same error trying to run the program on an FPGA. I also tried initializing pac_a10_usm which fails, but since it is not the default board variant I don't believe it is a factor here.
I've been using the "Hough_Transform_on_FPGAs_Using_oneAPI" jupyter notebook as a guide for the process. Not too sure on how to share it since it was just included in my user folder. The specific notebook I am referencing should be located at "~/Hough_Transform_on_FPGAs_Using_oneAPI/03_FPGA_Bitstream_Compilation_Using_the_Intel_FPGA_Add-On_for_oneAPI_Base_Toolkit/FPGA_Bitstream_Compilation_Using_the_Intel_FPGA_Add-On_for_oneAPI_Base_Toolkit.ipynb".
I think have shared the steps I am doing for compilation and the nodes I have been trying to run on above. If there's some piece which seems missing feel free to let me know.
Hi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Thank you.
