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DE10-nano does not boot with OpenCL image 18.1

g_flamis
Beginner
949 Views

Hello,

I am using the OpenCL image version 18.1 to my DE10-nano and several times to boot freeze at:

mmc0: new SDHC card at address 0001
mmcblk0: mmc0:0001 SD16G 7.44 GiB
mmcblk0: p1 p2 p3
EXT3-fs (mmcblk0p2): error: couldn't mount because of unsupported optional features (240)
EXT2-fs (mmcblk0p2): error: couldn't mount because of unsupported optional features (240)
EXT4-fs (mmcblk0p2): warning: mounting unchecked fs, running e2fsck is recommended
EXT4-fs (mmcblk0p2): mounted filesystem without journal. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 364K (806c9000 - 80724000)

 

 

 

 

 

 

 

 

 

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7 Replies
BoonBengT_Intel
Moderator
863 Views

Hi @g_flamis,


Thank you for posting in Intel community forum and hope all is well.

Mind if I asked what are the design you are implementing? Or any link to the referenes design followed?

If possible what are the command executed which cause the boot freeze?

Hope to hear from you soon.


Best Wishes

BB


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gflamis
Beginner
823 Views

Hi BB,

the problem seems to appear at the early stages before boot is completed. I aim to use this setup for deploying a machine learning model in OpenCL. My project work is based on InnovateFPGA contest (EM042). The DE10-nano I am using has been received from Terasic support and I am trying with 18.1 staff from here.

 

Thank you

Giorgos    

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BoonBengT_Intel
Moderator
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Hi @g_flamis,

If I understand correctly, based on the user guide (DE10_Nano_opencl_18.1.pdf) that you have downloaded from the terasic website, in the steps 1.4 where you are trying to execute the opencl demo in the board.


You are having boot up problem as below after writing the img to microSD and try to boot yes?

My guess it seems there seems to be some corruption in the microSD, perhaps try formatting or swapping another microSD. If also possible to try with another design just to check from hardware perspectives.

Hope that clarify.


Note: as design are coming from terasic would suggest to contact terasic support as we do not have visibilities on design development.


Best Wishes

BB


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gflamis
Beginner
760 Views

Hi BB,

thanks for the inputs, your understanding is correct.

I have already tried the same image with another SDcard and the behavior follows the image.

I did also used other images and the device boots properly, I did these before really deciding to post my ticket here.

It is understood that it might be outside of Intel's control space, but I really have to find a way of using my hardware effectively.

 

How would you advice me to move with more recent updates from Intel in using OpenCL with DE10-nano (Cyclone-V)? 

I have looked to the supporting material in Intel site, but I couldn't locate the exact features I should be using for the combination I am interested to use.

 

Thank you again

Giorgos

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BoonBengT_Intel
Moderator
732 Views

Hi @g_flamis,


Apologies for the delayed in response, unfortunately per my understanding BSP for DE series devices are only available in on terasic website.

However I do notice from the terasic guide that it seens that the img are just a prebuild file which is for the demo, there is no dependencies on the executing other project.

Hence there should be no problem in proceeding to use the BSP from terasic and running other opencl example of chapter 2 onwards.

Hope that clarify.


Best Wishes

BB


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gflamis
Beginner
707 Views

Hi BB,

no worries, I have communicated with Terasic and they provided us with instructions as similar issues are randomly met at their side, too. It looks like our case is a bit worse though and the problems are met more often, so they are sending as a replacement board.

For the history to mention that DE10-nano will boot properly when no cables are attached (ethernet, USB) and will remain operational since then. When the problem is met, it will recover some time later, like there is a capacitance loaded that has to be discharged.

Your suggestion is most probably right, building a new BPS, potentially with lower speed in memory access at boot would be a good solution. We were planing to use this setup for the InnovateFPGA challenge, but unfortunately we did not make it to meet the deadline.

Anyhow, please close this ticket...

Best Regards

Giorgos

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BoonBengT_Intel
Moderator
701 Views

Hi @g_flamis,


Thanks for sharing the finding on your end appreciate that, good to know that you have managed to overcome the challenges which in this case suspecting hardware related issues. Sorry to hear that the deadline is missed, hopefully there is another chances in the future.

Anyway thanks for the questions and as always pleasure having you here, will proceed to close the case.


Best Wishes

BB


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