Following an old question (https://forums.intel.com/s/question/0D50P00004MInzpSAD/double-pumping-dsp-units-ip) is there any way to allow double pumping of DSPs in Stratix 10 and to exploit this directly in OpenCL?
The OpenCL compiler does not support DSP double-pumping and in fact, even Block RAM double-pumping that was supported for older FPGAs (Stratix V and Arria 10) has been disabled for Stratix 10. Even though this would be a very useful feature since kernels on Stratix 10 tend to run at far lower frequencies than the promised 800-900 MHz, seeing how even the existing Block RAM double-pumping was disabled for Stratix 10, I would not expect DSP double-pumping to ever be supported. The option to implement DSP double-pumping manually in RTL and using it as an RTL blackbox in OpenCL theoretically exists, but it won't be easy to implement and I am not sure if the OpenCL compiler provides a 2x clock on Stratix 10 anymore (or at all).
Double pumping does work on S10. You can apply the attribute doublepump to request double pumping for a given array. Will request to have it on dsp for the future. Thanks
In your opinion, would it be possible to implement it as RTL block? Does OpenCL compiler/designs provide everything that I would need for that?
I could not find any useful documentation for this.
@KennyT_Intel This is not true, Section 10.3 of the documentation (https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807516407.html#jhl15202734...) clearly states that no 2x clock is provided in the design by the compiler for Stratix 10 and hence, Block RAM double-pumping is not available on Stratix 10. This also means that any type of double-pumping cannot be implemented by the user in RTL either since there is no 2x clock in the system generated by the compiler.
Thanks for pointing out, the attribute doublepump for Startix 10 should be working. The compiler may not infer double-pumping my default, but the attribute should always be able to override that.
Will have this documentation corrected.
Interesting; I just tested Block RAM double-pumping on Stratix 10 and indeed it seems to work. All this time I was thinking it won't work because the documentation said so. Having DSP double-pumping on top of that will be extremely valuable and a huge advantage over the main competitor's HLS compiler (among numerous other advantages that Intel's HLS compiler has). In fact, on Stratix 10 there is probably room to even do triple-pumping, considering how high the peak operating frequency of the Block RAMs and the DSPs is compared to typical kernel frequency.